Configurable I/O system using logic state arrays

A configurable I/O system, comprising

• an input state array for receiving a plurality of input signals and having a plurality of elements where each element respectively corresponds to one of said input signals;
• a latch array having elements for receiving and storing the states of the respective elements of the input state array;
• means for controlling a clock signal provided to the latch array to synchronize operation of an system with the occurrence of the clock signal;
• a multi-input AND array;
• an AND inverter array having elements for receiving and selectively inverting the elements of the latch means;
• an AND input selection array for selectively directing a corresponding bit from the AND inverter array into one of the inputs of the multi-input AND array;
• an AND output inverter for selectably inverting the output of the multi-input AND array;
• a multi-input OR array;
• an OR inverter array having elements for receiving and selectively inverting the elements of the latch means;
• an OR input selection array for directing a corresponding bit from the OR inverter array into one of the inputs of the multi-input OR array;
• an OR output inverter for selectably inverting the output of the multi-input OR array;
• an OR gate for combining the outputs of the AND output inverter and the OR output inverter;
• and
• an output means for outputting the output signal signals for the OR gate.

A configurable I/O system, comprising

• an input state array having input state variables acted upon by logic functional block arrays;
• a first Exclusive OR array for logically combining each respective element of the input state array with the respective elements of an AND invert array;
• a first AND array for logically combining each respective elements of the first Exclusive OR array with each respective elements of an And enable array;
• a first OR array for logically combining the respective elements of the AND array into a single element;
• a first Exclusive-OR invert Array for combining the single element of the OR array with an invert command signal to selectably provide an inverted or non-inverted AND output signal;
• a second Exclusive OR array for logically combining each respective element of the input state array with the respective elements of an OR Invert array;
• a second AND array for logically combining respective elements of the second Exclusive OR array with respective elements of an OR enable array;
• a second OR array for logically combining the respective elements of the second AND array into a single element;
• a second Exclusive-OR invert Array for combining the single element of the OR array with an invert command signal to selectably provide an inverted or non-inverted OR output signal and;
• an output OR function for logically combining the inverted or non-inverted AND output signal with the inverted or non-inverted OR output signal to provide an output signal.