Architecture and method for sharing TLB entries through process IDS

An address translation control circuit configured to operate in connection with a processor and a translation look-aside buffer that includes a translation table having at least one translation table entry including a pre-stored virtual address and a context identification number and also configured to translate a requested virtual address from the processor into a physical address, the address translation control circuit comprising:

• a primary context storage element configured to store a first context number;
• a group context storage element configured to store a second context number;
• a context matching circuit configured to receive said first context number from said primary context storage element, said second context number from said group context storage element and said context identification number from the at least one translation table entry and to output at least one context matching signal indicating whether said context identification number is equivalent to a selected context number being one of said first and second context numbers;
• a comparing unit configured to compare the pre-stored virtual address with the requested virtual address and to output a comparison signal indicating whether the pre-stored virtual address is equivalent to the requested virtual address;
• and
• a logic unit coupled to said context matching circuit and said comparing unit, said logic unit being configured to output a translation Hit signal if said context matching signal indicates that said context identification number is equivalent to said selected context number and said comparison signal indicates that the pre-stored virtual address is equivalent to the requested virtual address.

A computer system comprising:

• a bus;
• and
• a processing unit coupled to said bus, said processing unit including
• a processor configured to issue a request to translate a requested virtual address into a physical address, and
• a memory management unit coupled to said processor, said memory management unit including
• a translation look-aside buffer including a translation table, said translation table having at least one translation table entry including a pre-stored virtual address and a context identification number, and
• an address translation control circuit configured to (i) receive a first context number, a second context number and said context identification number and (ii) output a translation Hit signal to indicate that the translation look-aside buffer is currently storing the physical address when said context identification number is equivalent to a selected context number being one of said first and second context numbers and the pre-stored virtual address is equivalent to the requested virtual address.

A computer system comprising:

• a bus;
• and
• a processing unit coupled to said bus, said processing unit including
• a processor requesting translation of a requested virtual address, and
• a memory management unit coupled to said processor, said memory management unit including
• a translation look-aside buffer including a translation table, said translation table having at least one translation table entry including a pre-stored virtual address and a context identification number, and
• an address translation control circuitry, said address translation control circuit including
• a primary context storage element configured to contain a first context number,
• a group context storage element configured to contain a second context number,
• a context matching circuit configured to receive said first context number from said primary context storage element, said second context number from said group context storage element and said context identification number from the at least one translation table entry and to output at least one context matching signal indicating whether said context identification number is equivalent to a selected context number being one of said first and second context numbers,
• a comparing unit configured to compare the pre-stored virtual address with the requested virtual address and to output a comparison signal indicating whether the pre-stored virtual address is equivalent to the requested virtual address, and
• a logic unit coupled to said context matching circuit and said comparing unit, said logic unit being configured to output a translation Hit signal if said context matching signal indicates that said context identification number is equivalent to said selected context number and said comparison signal indicates that the pre-stored virtual address is equivalent to the requested virtual address.

A method for translating a virtual address from an electronic device to a physical address through the use of a translation look-aside buffer, the method comprising the steps of:

• loading a first context number into a primary context storage element;
• loading a second context number into a group context storage element;
• obtaining a tag portion of a translation table entry of a translation table of the translation look-aside buffer associated with the virtual address, said tag portion including a context select bit, a context identification number and a pre-stored virtual address;
• selecting one of said first and second context numbers;
• comparing said one of said first and second context numbers to said context identification number;
• comparing said pre-stored virtual address to the virtual address;
• transmitting a translation Hit signal, provided (i) said one of said first and second context numbers is equivalent to said context identification number and (ii) said pre-stored virtual address is equivalent to the virtual address.