Single-edge triggered phase detector
AssigneesAT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.
InventorsDao-Long Chen, Robert D. Waldron
Life of this patent
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Abstract
A single-edge triggered phase detector which provides high speed phase detection. The phase detector works on only a single edge of the clock and data signal, which can be either the rising or falling edge. Extracted control signals are latched for at least one half of a clock period or more to ensure full rail to rail swing.
Claims36
A method for adjusting a clock signal, comprising the steps of:
- detecting a unipolar transition on a data signal;
- detecting at least one unipolar transition on said clock signal;
- and
- adjusting said clock signal, in response to said detected data signal unipolar transition and said at least one detected clock signal unipolar transition, by a plurality of control signals comprising a first signal and a second signal different from the first signal, said first and second signals each having a minimum pulse width of at least one half clock period of the clock signal to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
A method for generating a plurality of controls signals used to adjust a clock signal, said plurality of control signals comprising a first signal and a second signal different from the first signal, comprising the steps of:
- detecting a unipolar transition on a data signal;
- detecting at least one unipolar transition on said clock signal;
- and
- generating said first and second control signals, each having a minimum pulse width of at least one half clock period of the clock signal, in response to said detected data signal unipolar transition and said at least one detected clock signal unipolar transition to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
A method for generating a plurality of control signals in a system having at least one data signal and at least one clock signal, said plurality of control signals comprising a first signal and a second signal different from the first signal, and said data and clock signals comprising a plurality of rising and falling edge transitions, comprising the steps of:
- detecting a single edge transition of said data signal;
- detecting a first single edge transition of said clock signal;
- detecting a second single edge transition, having a same polarity as the first single edge transition, of said clock signal;
- and
- generating said first and second control signals, each having a minimum pulse width of at least one half clock period of the clock signal, in response to said detected data signal transition and said detected first and second clock signal transitions, to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
A method for generating a plurality of control signals by a phase detector, comprising the steps of:
- activating a first control signal upon detection of a unipolar transition on a data signal;
- activating a second control signal and deactivating said first control signal upon detection by said phase detector of a unipolar transition on said clock signal, said phase detector having an input for directly receiving said clock signal;
- and
- deactivating said activated second control signal upon detection by said phase detector of a subsequent unipolar transition on said clock signal.
A method for generating a plurality of control signals by a phase detector, comprising the steps of:
- latching a first control signal upon detection of an active data signal;
- latching a second control signal and resetting said first control signal upon detection by said phase detector of an active clock signal, said phase detector having an input for directly receiving said active clock signal;
- and
- resetting said latched second control signal upon detection by said phase detector of a subsequent active clock signal.
A phase detector, comprising:
- data means for detecting a unipolar transition on a data signal;
- clock means for detecting at least one unipolar transition on a clock signal;
- and
- means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal to phase lock a subsequent transition of the data signal and clock signal coincident with each other.
A phase locked loop circuit, comprising a voltage controlled oscillator and a phase detector, wherein said phase detector further comprises:
- data means for detecting a unipolar transition on a data signal;
- clock means for detecting at least one unipolar transition on a clock signal;
- and
- means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
A phase locked loop circuit, comprising a phase detector, wherein said phase detector further comprises:
- data means for detecting a unipolar transition on a data signal;
- clock means for detecting at least one unipolar transition on a clock signal;
- means, coupled to said data means and said clock means, for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of the clock signal;
- and
- means, coupled to said plurality of control signals, for adjusting phase of said clock signal to coincide a subsequent data signal unipolar transition and clock signal unipolar transition.
A system for generating a plurality of control signals, comprising a phase detector circuit having an input for directly receiving a clock signal, said phase detector circuit comprising:
- means for activating a first control signal upon detection of a unipolar transition on a data signal;
- means for activating a second control signal, and deactivating said first control signal, upon detection by said phase detector of a unipolar transition on said clock signal;
- and
- means for deactivating said activated second control signal upon detection by said phase detector of a subsequent unipolar transition on said clock signal.
A phase detector circuit for generating a plurality of control signals, said phase detector circuit having an input for directly receiving a clock signal, comprising:
- means for latching a first control signal upon detection of an active signal level of a data signal;
- means for latching a second control signal and resetting said first control signal upon detection by said phase detector circuit of an active signal level of said clock signal;
- and
- means for resetting said latched second control signal upon detection by said phase detector circuit of a subsequent active clock signal.
A phase detector, comprising:
- a unipolar data signal transition detector circuit;
- a unipolar clock signal transition detector circuit for detecting a unipolar transition of said clock signal;
- a control signal generation circuit coupled to said unipolar data signal transition detector circuit and said unipolar clock signal transition detector circuit for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of said clock signal;
- and
- means for synchronizing a subsequent data signal transition and subsequent clock signal transition coincident with each other.
A phase locked loop circuit, comprising a voltage controlled oscillator and a phase detector, wherein said phase detector further comprises:
- a unipolar data signal transition detector circuit;
- a unipolar clock signal transition detector circuit for detecting a unipolar transition of said clock signal;
- a control signal generation circuit coupled to said unipolar data signal transition detector circuit and said unipolar clock signal transition detector circuit for generating a plurality of control signals comprising a first signal and a second signal different from the first signal, the first and second signals each having a minimum pulse width of at least one half clock period of said clock signal;
- and
- means for synchronizing at least one subsequent data and clock signal coincident with each other.
A method for adjusting a clock signal, comprising the steps of:
- detecting a unipolar transition on a data signal comprising a plurality of transitioning data values and a plurality of consecutive same value data values;
- detecting at least one unipolar transition on said clock signal;
- and
- adjusting said clock signal in response to said detected data signal unipolar transition and said detected clock signal unipolar transition by generating a first control signal having a fixed pulse width equal to a clock period of said clock signal and a second control signal having pulse width dependent upon the relative phase relationship between the data signal and clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
A phase detector, comprising:
- data means for detecting a unipolar transition on a data signal comprising a plurality of transitioning data values and a plurality of consecutive same value data values;
- clock means for detecting a unipolar transition on said clock signal;
- and
- means, coupled to said data means and said clock means, for adjusting said clock signal by generating a first control signal having a fixed pulse width equal to a clock period of said clock signal and a second control signal having pulse width dependent upon the relative phase relationship between the data signal and clock signal, to synchronize a subsequent transition of the data signal and clock signal coincident with each other.
Dependencies are inferred from the claim text.