Translation look-aside buffer including a single page size translation unit
AssigneeIntel Corporation
InventorGary N. Hammond
Life of this patent
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Abstract
A method and apparatus for use in a computer system to translate virtual addresses into translated addresses. According to one aspect of the invention, a dynamically configurable translation unit is provided. Based on a value stored in a storage area, the dynamically configurable translation unit configures itself to support the single page size identified by the value. In one computer system, the dynamically configurable translation unit is used in conjunction with a multiple page size translation unit.
Claims20
A translation look-aside buffer comprising:
- a first storage area to store a dynamic value identifying a single page size;
- a first translation unit to simultaneously store virtual to physical address translations for a plurality of page sizes;
- and
- a second translation unit to store virtual to physical address translations for only the single page size identified by said dynamic value.
A computer system comprising:
- an execution unit generating a first virtual address and a second virtual address;
- a first storage area having stored therein a dynamic value identifying one of a first page size and a second page size;
- a first translation unit having stored therein a first translation and a second translation, said first translation for translating said first virtual address into a first translated address identifying a first location in a first page of said first page size, said second translation for translating said second virtual address into a second translated address identifying a second location in a second page of said second page size;
- and
- a second translation unit dynamically configured to translate only one of said first virtual address and said second virtual address based on said dynamic value.
An apparatus for use in a computer system comprising:
- an execution unit to generate virtual addresses;
- a first translation unit, coupled to said execution unit, including a fully associative cache to simultaneously store address translations for a plurality of page sizes;
- and
- a second translation unit, coupled to said execution unit, including a set associative cache to store address translations for a single page size.
A computer system comprising:
- a processor;
- a storage device coupled to said processor;
- a translation look-aside buffer comprising:
- a first translation unit, in said processor, to simultaneously store virtual to physical address translations for a plurality of page sizes, and
- a second translation unit to store virtual to physical address translations for only a single page size in said storage device;
- and
- a TLB miss handler, in said storage device, coupled to said translation look-aside buffer.
A method for translating a virtual address into a physical address, said method comprising the computer-implemented steps of:
- configuring a first translation unit to provide virtual to physical address translations for a single page size;
- determining if a translation for said virtual address is stored in said first translation unit or a second translation unit, said second translation unit providing virtual to physical address translations for multiple page sizes;
- if said translation is not in either said first translation unit or said second translation unit, then executing a translation look-aside buffer miss handler;
- and
- translating said virtual address into said physical address using said translation.
Dependencies are inferred from the claim text.