Distributed processing memory chip with embedded logic having both data memory and broadcast memory

A computer system, comprising:

• a central processing unit;
• a memory system, said memory system including a plurality of memory integrated circuits (ICs), each of said memory ICs including:
• a data memory, said data memory coupled to a data bus terminal;
• a chip select terminal coupled to said data memory for receiving a signal from said central processing unit;
• a broadcast memory, said broadcast memory coupled to said data bus terminal, and said broadcast memory not coupled to said chip select terminal, wherein the broadcast memories from more than one of said memory ICs respond simultaneously to a single broadcast write from said central processing unit;
• an address bus terminal directly coupled to said data memory and broadcast memory;
• a datapath coupled to both said data memory and said broadcast memory;
• and
• input/output circuitry for connecting said central processing unit and said memory system.