Method of synchronizing a pair of central processor units for duplex, lock-step operation by copying data into a corresponding locations of another memory

In a computing system including first and second processor elements of substantially identical construction coupled to one another for communicating data therebetween, each of the first and second processor elements including a memory element for storing instructions and data, the first processor element operating to execute instructions of an instruction stream from the memory element of the first processor element, a method for establishing for synchronized, substantially lock-step operation of the second processor element with the first processor element to have the second processor element executing the same instructions at substantially the same moment in time as the first processor element, the method including the steps of:

• operating the second processor element in synchronization with the first processor element;
• the first processor element accessing the instructions and data of the memory element of the first processor element and communicating the accessed instructions and data to the second processor element with address data indicative of locations in the memory element of the second processor element corresponding to locations at which the instructions and data are stored in the memory element of the first processor element;
• storing the received instructions and data in the memory element of the second processor element at the locations indicated by the address data;
• marking first locations of the memory element of the first processor that are written with new data or new instructions after the instructions and data accessed from the first locations for communication to the second processor element;
• and
• periodically reviewing the memory element of the first processor element to locate marked first locations to send the instructions or data contained in said located marked first locations for storing in the memory element of the second processor element at locations corresponding to location of the first memory element.