Fail-fast, fail-functional, fault-tolerant multiprocessor system

A processing system, comprising:

• at least a pair of central processing means for performing data processing functions;
• a plurality of peripheral elements;
• and
• routing means having a plurality of ports coupled to the pair of central processing means and to the plurality of peripheral elements for communicating data therebetween, each of the plurality of ports being configured to provide simultaneous bi-directional communication;
• whereby the routing means is operable to provide a first communication path between the pair of central processing means and a plurality of second communication paths between either one of the pair of central processing means and any one of the plurality of peripheral elements.

A processing system, comprising:

• a pair of central processing units each including at least a pair of processor elements configured to operate in lock-step, self-checking configuration to execute a stream of instructions, the pair of central processor units being configured to operate in a first mode whereby a one of the pair of central processing units executes instructions that are different from instructions executed by the other of the pair of central processing units, and a second mode in which the pair of central processor units operate in a lock-step mode to executed substantially the same instructions at substantially the same time;
• first and second router elements each coupled to communicate data with the pair of central processing units;
• and
• at least first and second peripheral units respectively coupled to the first and second router elements;
• wherein the first and second router elements are operable, when the pair of central processor units are in the second mode, to communicate data from the first or the second peripheral units to both the pair of central processor units substantially simultaneously.

A data processing system, comprising:

• at least a pair of central processing units, each of the pair of central processing units having first and second data ports for receiving and transmitting data;
• at least first and second peripheral control units for receiving and sending data;
• and
• a first routing element having a number of ports whereat data is received and transmitted, each of a pair of the number of ports being coupled to the first data ports of the pair of central processing units, another of the number of ports being coupled to at least the first peripheral control unit;
• and
• a second routing element having a number of ports whereat data is received and transmitted, each of a pair of the number of ports being coupled to the first data ports of the pair of central processing units, another of the number of ports being coupled to at least the second peripheral control unit.

A data processing system, comprising:

• at least two sub-processing systems, each sub-processing system including;
• a central processing unit, including at least a pair of processor elements operating in lock-step, self-checking configuration, and executing substantially identical instructions at substantially the same time, the central processing unit of each of the two sub-processing systems being operable in a first mode independent of one another to execute instructions of different instruction streams, and a second mode in which the central processing unit of each of the two sub-processing systems operate in lock-step synchronism to execute the same instructions at substantially the same time,
• a peripheral unit, and
• a routing element coupled to the central processing unit of each of the sub-processing systems and to the peripheral unit for communicating data between the central processing units and peripheral unit of the sub-processing systems the routing element including means to communicate data from the peripheral unit to both central processing units substantially at the same time when the central processing units are operating in the second mode;
• the central processing unit including data synchronization means coupled to receive the data from the routing elements of each sub-processing system for synchronizing the received data for presentation to each of the central processor units at substantially the same time when the central processing units are operating in the second mode, the data synchronization means including temporary storage means having a plurality of storage locations for storing data received from the routing elements, first addressing means operated by the routing elements to store data from the routing elements in the temporary storage means, and second addressing means operated by the central processing unit to remove data from the temporary storage means.

A data processing system, comprising:

• at least two sub-processing systems, each sub-processing system including;
• (a) a central processing unit, each central processing unit including at least a pair of processor elements operating in lock-step, self-checking configuration, and executing substantially identical instructions at substantially the same time, a peripheral unit, and
• (b) a routing element coupled to the central processing unit of each of the sub-processing systems and to the peripheral unit for communicating data between the central processing units and peripheral unit of the sub-processing systems, the data being communicated between the central processing units and the peripheral units of each sub-processing system in the form of one or more message packets each containing multiple ones of multi-bit data words, and wherein the message packets each contain information identifying the source and destination of the message packets;
• and
• (c) the central processing unit including a memory element having an access validation table that is used in response to receipt of the message packets to inspect the source and destination information and determine therefrom whether data will be allowed to be read from or written to the memory means.