# US 5,751,634 A · Non-volatile semiconductor memory device for storing multivalue data and readout/write-in method therefor > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,751,634 A - Document ID: US5751634A - Status: Granted - Kind: A - Application number: 08/647,629 - Filed: 1996-05-15 - Granted: 1998-05-12 - Earliest claimed: 1995-05-16 - Assignees: Kabushiki Kaisha Toshiba - Inventors: Yasuo Itoh - Web page: https://patentgrep.com/patent/US5751634A ## CPC - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 11/5621: {using charge storage in a floating gate} - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 2211/5642: Multilevel memory with buffers, latches, registers at input or output - G11C 2211/5647: Multilevel memory with bit inversion arrangement - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory cells each for storing 2-bit data are connected to a bit line. First and second flip-flop circuits are coupled to the bit line. The first flip-flop circuit holds the lower bit of 2-bit data read out from or written into the memory cell and the second flip-flop circuit holds the upper bit of 2-bit data read out from or written into the memory cell. At the data readout time, the upper bit is first read out from the memory cell and then the lower bit is read out from the memory cell. At the data writing time, the upper bit is first written into the memory cell and then the lower bit is written into the memory cell. ## Claims ### Claim 1 A non-volatile semiconductor memory device comprising: memory cells connected to bit lines, first and second data being stored in each of said memory cells; a voltage generating circuit for generating a plurality of reference voltages of different levels and supplying the reference voltages to the gates of said memory cells at the time of data writing and data readout; and first and second storage circuits coupled to each of said bit lines, for holding first and second data to be written into one of said memory cells at the data writing time and holding first and second data read out from said memory cell according to the plurality of reference voltages at the data readout time. ### Claim 2 (depends on 1) A device according to claim 1, wherein each of said memory cells stores plural-bit data, the first data is lower-bit data, and the second data is upper-bit data. ### Claim 3 (depends on 2) A device according to claim 2, wherein said memory cells are arranged in NAND cell units. ### Claim 4 (depends on 1) A device according to claim 1, wherein each of said first and second storage circuits comprises a flip-flop circuit. ### Claim 5 (depends on 2) A device according to claim 2, further comprising a transfer circuit connected to said first and second storage circuits, for transferring the upper-bit data stored in said second storage circuit to said first storage circuit at the time of readout of the lower-bit data. ### Claim 6 A non-volatile semiconductor memory device comprising: memory cells connected to bit lines and each having a control gate and a floating gate, each of said memory cells having one of first, second, third and fourth threshold voltages which are set at different levels; a voltage generating circuit for generating first, second and third reference voltages and for supplying one of the reference voltages to the control gates of said memory cells at the data readout time, the level of the first reference voltage being set between the first and second threshold voltages, the level of the second reference voltage being set between the second and third threshold voltages, and the level of the third reference voltage being set between the third and fourth threshold voltages; and first and second storage circuits coupled to each of said bit lines, said second storage circuit holding one of first data corresponding to the first or second threshold voltage which is lower than the second reference voltage and second data corresponding to the third or fourth threshold voltage which is higher than the second reference voltage at the data readout time, and said first storage circuit holding one of third data corresponding to the first threshold voltage which is lower than the first reference voltage, fourth data corresponding to the second threshold voltage which is higher than the first reference voltage, fifth data corresponding to the third threshold voltage which is lower than the third reference voltage, and sixth data corresponding to the fourth threshold voltage which is higher than the third reference voltage. ### Claim 7 (depends on 6) A device according to claim 6, wherein each of the first and second data is upper-bit data and each of the third to sixth data is lower-bit data. ### Claim 8 (depends on 6) A device according to claim 6, wherein said memory cells are arranged in NAND cell units. ### Claim 9 (depends on 6) A device according to claim 6, wherein each of said first and second storage circuits comprises a flip-flop circuit. ### Claim 10 (depends on 6) A device according to claim 6, further comprising a transfer circuit connected to said first and second storage circuits, for transferring the second data stored in said second storage circuit to said first storage circuit at the time of readout of the fifth, or sixth data. ### Claim 11 A non-volatile semiconductor memory device comprising: memory cells connected to bit lines and each having a control gate and a floating gate, each of said memory cells having one of first, second, third and fourth threshold voltages which are set at different levels; a voltage generating circuit for generating first, second and third reference voltages and for supplying one of the reference voltages to the control gates of said memory cells at the data writing time, the level of the first reference voltage being set between the first and second threshold voltages, the level of the second reference voltage being set between the second and third threshold voltages, and the level of the third reference voltage being set between the third and fourth threshold voltages; and first and second storage circuits coupled to each of said bit lines, said second storage circuit holding one of first data corresponding to the first or second threshold voltage which is lower than the second reference voltage and second data corresponding to the third or fourth threshold voltage which is higher than the second reference voltage at the data writing time, and said first storage circuit holding one of third data corresponding to the first threshold voltage which is lower than the first reference voltage, fourth data corresponding to the second threshold voltage which is higher than the first reference voltage, fifth data corresponding to the third threshold voltage which is lower than the third reference voltage, and sixth data corresponding to the fourth threshold voltage which is higher than the third reference voltage; wherein the first data held in said second storage circuit is written into one of the memory cells with the second reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the first threshold voltage, the second data held in said second storage circuit is written into the memory cell with the second reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the third threshold voltage, the third data held in said first storage circuit is written into the memory cell with the first reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the first threshold voltage, the fourth data held in said first storage circuit is written into the memory cell with the first reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the second threshold voltage, the fifth data held in said first storage circuit is written into the memory cell with the third reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the third threshold voltage, and the sixth data held in said first storage circuit is written into the memory cell with the third reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the fourth threshold voltage. ### Claim 12 (depends on 11) A device according to claim 11, wherein each of the first and second data items is upper-bit data and each of the third to sixth data items is lower-bit data. ### Claim 13 (depends on 11) A device according to claim 11, wherein said memory cells are arranged in NAND cell units. ### Claim 14 (depends on 11) A device according to claim 11, wherein each of said first and second storage circuits comprises a flip-flop circuit. ### Claim 15 (depends on 11) A device according to claim 11, further comprising a transfer circuit connected to said first and second storage circuits, for transferring the fourth data stored in said first storage circuit to said second storage circuit at the time of writing of the fourth data. ### Claim 16 (depends on 11) A device according to claim 11, further comprising an inverting type reading circuit connected to said first storage circuit and said bit line, for reading out data stored in the memory cell, inverting the readout data and then storing the inverted readout data into said first storage circuit. ### Claim 17 A non-volatile semiconductor memory device comprising: memory cells connected to bit lines and each having a control gate and a floating gate, each of said memory cells having one of first, second, third and fourth threshold voltages which are set at different levels; a first storage circuit coupled to each of said bit lines; a second storage circuit coupled to each of said bit lines; and a voltage generating circuit for generating first, second and third reference voltages and for supplying one of the reference voltages to the control gates of said memory cells, the level of the first reference voltage being set between the first and second threshold voltages, the level of the second reference voltage being set between the second and third threshold voltages, and the level of the third reference voltage being set between the third and fourth threshold voltages; wherein said first storage circuit detects whether one of the first to fourth threshold voltages read out from the memory cell is lower or higher than the second reference voltage, holds the result of detection, said second storage circuit detects whether the readout threshold voltage is lower or higher than the first reference voltage when the readout threshold voltage is lower than the second reference voltage and holds the result of detection, and detects whether the readout threshold voltage is lower or higher than the third reference voltage when the readout threshold voltage is higher than the second reference voltage and holds the result of detection. ### Claim 18 (depends on 17) A device according to claim 17, wherein said memory cells are arranged in NAND cell units. ### Claim 19 (depends on 17) A device according to claim 17, wherein each of said first and second storage circuits comprises a flip-flop circuit. ### Claim 20 (depends on 17) A device according to claim 17, further comprising a transfer circuit connected to said first and second storage circuits, for transferring the second data stored in said second storage circuit to said first storage circuit at the time of readout of the fifth and sixth data. ### Claim 21 (depends on 17) A device according to claim 17, further comprising transfer circuits respectively connected to said first and second storage circuits, for respectively transferring data held in said first and second storage circuits to a data line. ### Claim 22 A readout method for reading out data from a memory cell in which one of first, second, third and fourth threshold voltages whose levels are set in the ascending order is set, comprising the steps of: storing first data into a first storing circuit when a voltage read out from the memory cell to a bit line corresponds to the first or second threshold voltage which is lower than the second reference voltage and storing second data into said first storing circuit when a voltage read out from the memory cell to the bit line corresponds to the third or fourth threshold voltage which is higher than the second reference voltage; and storing third data into a second storing circuit when a threshold voltage read out from the memory cell to the bit line corresponds to the first threshold voltage which is lower than the first reference voltage, storing fourth data into said second storing circuit when a threshold voltage read out from the memory cell to the bit line corresponds to the second threshold voltage which is higher than the first reference voltage, storing fifth data into said second storing circuit when a threshold voltage read out from the memory cell to the bit line corresponds to the third threshold voltage which is lower than the third reference voltage, and storing sixth data into said second storing circuit when a threshold voltage read out from the memory cell to the bit line corresponds to the fourth threshold voltage which is higher than the third reference voltage. ### Claim 23 (depends on 22) A method according to claim 22, wherein each of the first and second data items is upper-bit data, each of the third to sixth data items is lower-bit data, and the lower-bit data is read out after the upper-bit data is read out at the data readout time. ### Claim 24 A data writing method for writing one of first, second, third and fourth threshold voltages whose levels are set in the ascending order is set into a memory cell, comprising the steps of: holding one of first data corresponding to the first or second threshold voltage and second data corresponding to the third or fourth threshold voltage in a second storage circuit; holding one of third data corresponding to the first threshold voltage, fourth data corresponding to the second threshold voltage, fifth data corresponding to the third threshold voltage, and sixth data corresponding to the fourth threshold voltage in a first storage circuit; and generating one of first, second and third reference voltages and supplying the reference voltage to the gate of the memory cell, the level of the first reference voltage being set between the first and second threshold voltages, the level of the second reference voltage being set between the second and third threshold voltages, and the level of the third reference voltage being set between the third and fourth threshold voltages; wherein the first data held in the first storage circuit is written into the memory cell with the second reference voltage used as a reference voltage to set the threshold voltage of the memory cell equal to the first threshold voltage, the second data held in the first storage circuit is written into the memory cell with the second reference voltage used as a reference voltage to set the threshold voltage of said memory cell equal to the third threshold voltage, the third data held in the second storage circuit is written into the memory cell with the first reference voltage used as a reference voltage to set the threshold voltage of the memory cell equal to the first threshold voltage, the fourth data held in the second storage circuit is written into the memory cell with the first reference voltage used as a reference voltage to set the threshold voltage of the memory cell equal to the second threshold voltage, the fifth data held in the second storage circuit is written into the memory cell with the third reference voltage used as a reference voltage to set the threshold voltage of the memory cell equal to the third threshold voltage, and the sixth data held in the second storage circuit is written into the memory cell with the third reference voltage used as a reference voltage to set the threshold voltage of the memory cell equal to the fourth threshold voltage. ### Claim 25 (depends on 24) A method according to claim 24, wherein each of the first and second data items is upper-bit data, each of the third to sixth data items is lower-bit data, and the lower-bit data is written after the upper-bit data is written at the data writing time. ### Claim 26 A non-volatile semiconductor memory device, comprising: memory cells connected to a bit line, each memory cell storing multi-bit data; selecting circuitry for selecting a memory cell; and first and second storing circuits connected to said bit line, said first storing circuit storing a first bit of the multi-bit data of the selected memory cell at a read-out time and a writing time and said second storing circuit storing a second bit of the multi-bit data of the selected memory cell at the read-out time and the writing time. ### Claim 27 (depends on 26) A device according to claim 26, further comprising: a transfer circuit for selectively transferring data between said first and second storage circuits. ### Claim 28 (depends on 27) A device according to claim 27, wherein said transfer circuit comprises: a first transistor having a first end coupled to said first storing circuit and a gate supplied with a first signal; a second transistor having a first end coupled to a second end of said first transistor, a second end coupled to a predetermined potential, and a gate supplied with a second signal; and a third transistor having a first end coupled to said second storing circuit, a second end coupled to the predetermined potential, and a gate coupled to a node between said first and second transistors. ### Claim 29 (depends on 26) A device according to claim 26, wherein each of said first and second storing circuits comprises a flip-flop circuit. ### Claim 30 (depends on 26) A device according to claim 26, wherein said memory cells are arranged in NAND cell units. ### Claim 31 (depends on 26) A device according to claim 26, wherein said multi-bit data is 2-bit data. ### Claim 32 A non-volatile semiconductor memory device, comprising: first memory cells connected to a first bit line, each first memory cell storing multi-bit data; second memory cells connected to a second bit line, each second memory cell storing multi-bit data; selecting circuitry for selecting one of said first and second memory cells; and first and second storing circuits connected to said first bit line and to said second bit line, said first storing circuit storing a first bit of the multi-bit data of the selected memory cell at a read-out time and a writing time and said second storing circuit storing a second bit of the multi-bit data of the selected memory cell at the read-out time and the writing time. ### Claim 33 (depends on 32) A device according to claim 32, further comprising: a transfer circuit for selectively transferring data between said first and second storing circuits. ### Claim 34 (depends on 33) A device according to claim 33, wherein said transfer circuit comprises: a first transistor having a first end coupled to said first storing circuit and a gate supplied with a first signal; a second transistor having a first end coupled to a second end of said first transistor, a second end coupled to a predetermined potential, and a gate supplied with a second signal; and a third transistor having a first end coupled to said second storing circuit, a second end coupled to the predetermined potential, and a gate coupled to a node between said first and second transistors. ### Claim 35 (depends on 32) A device according to claim 32, wherein each of said first and second storing circuits comprises a flip-flop circuit. ### Claim 36 (depends on 32) A device according to claim 32, wherein said first and said second memory cells are arranged in NAND cell units. ### Claim 37 (depends on 32) A device according to claim 32, further comprising: a first selecting transistor coupled between said first bit line and said first and second sense amplifiers; and a second selecting transistor coupled between said second bit line and said first and second sense amplifiers. ### Claim 38 A non-volatile semiconductor memory device, comprising: memory cells connected to a bit line; selecting circuitry for selecting said memory cells; first and second sense amplifiers coupled to said bit line, said first sense amplifier comprising a first storing circuit and said second sense amplifier comprising a second storing circuit; and a transfer circuit for selectively transferring data between said first storing circuit and said second storing circuit. ### Claim 39 (depends on 38) A device according to claim 38, wherein said transfer circuit comprises: a first transistor having a first end coupled to said first storing circuit and a gate supplied with a first signal; a second transistor having a first end coupled to a second end of said first transistor, a second end coupled to a predetermined potential, and a gate supplied with a second signal; and a third transistor having a first end coupled to said second storing circuit, a second end coupled to the predetermined potential, and a gate coupled to a node between said first and second transistors. ### Claim 40 (depends on 38) A device according to claim 38, wherein said memory cells are arranged in NAND cell units.