Non-volatile memory cell having dual gate electrodes
AssigneeSony Corporation
InventorsHiroshi Aozasa, Yutaka Hayashi
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Abstract
A non-volatile memory device in which gate electrodes are formed on an upper surface and a lower surface of the channel via insulating layers, respectively, one of them is used as a read electrode and the other is used as a write electrode, whereby, at a read operation the reading is carried out without exerting an influence upon stored charges stored at the time of writing. Particularly, it has a structure in which a source and drain region of the non-volatile semiconductor memory device in formed in the semiconductor layer formed on the insulating layer and, at the same time, one of the read electrode and write electrode is buried in the insulating layer.
Claims17
A non-volatile semiconductor memory device with reduced read disturb comprising:
- a semiconductor layer having a first surface and a second surface;
- a first insulating layer formed on said first surface and a second insulating layer formed on said second surface;
- and
- a first gate electrode formed on said first insulating layer and a second gate electrode formed on said second insulating layer;
- a charge storing means located in said first insulating layer;
- and
- a channel region formed in said semiconductor layer between said first gate electrode and said second gate electrode;
- wherein a thickness of said semiconductor layer at said channel region is such that a first electric field of said first surface of said semiconductor layer exerts an influence on a second electric field of said second surface of said semiconductor layer such that both a first gate threshold voltage measured with respect to said first gate electrode and a second gate threshold voltage measured with respect to said second gate electrode are changed by a charge stored in said charge storing means;
- and
- said thickness of said semiconductor layer "d" being determined by the following equation:
- d.ltoreq.(4.epsilon..phi..sub.F /qN.sub.B.sup.1/2
- where:
- .phi..sub.F =(kT/q)(1n(N.sub.B n.sub.i);
- .epsilon. is the dielectric constant of said semiconductor layer;
- q is the amount of the charge of an electron;
- N.sub.B is the concentration of impurities in said channel region;
- k is Boltzmann's constant;
- T is absolute temperature;
- and
- n.sub.i is the intrinsic carrier concentration of said semiconductor layer.
Dependencies are inferred from the claim text.