Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table

A data processor comprising:

• an instruction path;
• internal buses for operand and result data;
• a defined execution unit coupled to the internal buses and the instruction path for execution of defined instructions;
• a programmable execution unit coupled to the internal buses and the instruction path for execution of a set of programmed instructions;
• a condition code register connected to the programmable execution unit to receive condition codes from the programmable execution unit;
• and
• instruction management logic coupled with the instruction path which includes a store which stores identifiers for the set of programmed instructions, and matching logic which matches incoming instructions with the set to detect a programmed instruction miss in which an incoming instruction is not within the set.

A microprocessor, comprising:

• internal buses for operand and result data;
• a defined execution unit coupled to the internal buses for execution of defined instructions;
• a programmable execution unit coupled to the internal buses for execution of a set of programmed instructions;
• an instruction register which holds instructions in sequence for execution, and an instruction path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit;
• an instruction state machine, responsive to condition codes, which supply instructions to the instruction register;
• a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit;
• and
• instruction management logic coupled with the instruction path which includes a store which stores identifiers for the set of programmed instructions, and matching logic which matches incoming instructions with the set to detect a programmed instruction miss in which an incoming instruction is not within the set.

A data processor comprising:

• internal buses for operand and result data;
• a defined execution unit coupled to the internal buses for execution of defined instructions;
• a plurality of separately configurable execution units coupled to the internal buses for execution of respective sets of programmed instructions;
• and
• a configuration data bus coupled to at least one configurable execution unit whereby the at least one configurable execution unit is configured with data received from a source external to the data processor.