Method of damage free doping for forming a dram memory cell
AssigneeMosel Vitelic, Inc.
InventorsDer-Tsyr Fan, Chon-Shin Jou, Ting-S. Wang
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Abstract
A method of damage-free doping for forming a dynamic random access memory cell is disclosed herein. A phosphoric silicate glass is deposited as a diffusion source. The phosphorous ions of phosphoric silicate glass can be diffused into a substrate to form the source/drain regions by a high temperature during a thermal annealing process. Next, a thermal oxide layer is formed on the gate electrode and the surface of the substrate by the thermal oxidation process. The thermal oxide layer can prevent ions from diffusing into the substrate during the subsequent thermal treatment process. Therefore, the present invention can reduce the damage of a dynamic random access memory.
Claims19
A method of forming a dynamic random access memory comprising the steps of:
- forming a field oxide layer to define an active area;
- forming a gate oxide layer on a substrate;
- forming a polysilicon layer on said gate oxide layer;
- forming a photoresist layer on said polysilicon layer to define a gate electrode region;
- removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode;
- removing said photpresist layer;
- forming a dielectric layer on said gate electrode and said substrate;
- anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer;
- forming a phosphoric silicate glass on said gate electrode and said substrate;
- performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate;
- and
- performing thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode.
A method of forming a dynamic random access memory comprising the steps of:
- forming a field oxide layer to define an active area;
- forming a gate oxide layer on a substrate;
- forming a polysilicon layer on said gate oxide layer;
- forming a photoresist layer on said polysilicon layer to define a gate electrode region;
- removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode;
- removing said photpresist layer;
- forming a dielectric layer on said gate electrode and said substrate;
- anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer;
- forming a phosphoric silicate glass on said gate electrode and said substrate, the thickness of said phosphoric silicate glass being in a range of about 200 to 2000 angstroms;
- performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate, the temperature of said annealing process being about 800.degree. C. to 110.degree. C., the time of said annealing process being about 5 seconds to 1 hour;
- performing a dry thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode, the thickness of said thermal oxide layer being in a range of about 50 to 200 angstroms;
- removing said phosphoric silicate glass layer by a wet etching process using 1% hydrofluoric acid solution;
- and
- performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory.
A method of forming a dynamic random access memory comprising the steps of:
- forming a field oxide layer to define an active area;
- forming a gate oxide layer on a substrate;
- forming a polysilicon layer on said gate oxide layer;
- forming a photoresist layer on said polysilicon layer to define a gate electrode region;
- removing a portion of said polysilicon layer and said gate oxide layer using said photoresist as an etching mask to form a gate electrode;
- removing said photpresist layer;
- forming a dielectric layer on said gate electrode and said substrate;
- anisotropic etching said dielectric layer to form sidewall spacers on the sidewalls of said dielectric layer;
- forming a phosphoric silicate glass on said gate electrode and said substrate, the thickness of said phosphoric silicate glass being in a range of about 200 to 2000 angstroms;
- performing an annealing process to form a source and a drain regions by the phosphorous ions of said phosphoric silicate glass diffusing into said substrate, the temperature of said annealing process being about 800.degree. C. to 110.degree. C., the time of said annealing process being about 5 seconds to 1 hour;
- removing said phosphoric silicate glass layer by a dry etching process;
- performing a heavily doped process to MOS transistors of a periphery circuit in said dynamic random access memory;
- and
- performing a dry thermal oxidation process to form a thermal oxide layer on said substrate and said gate electrode, the thickness of said thermal oxide layer being in a range of about 50 to 200 angstroms.
Dependencies are inferred from the claim text.