Method for manufacturing ISRC MOSFET

A method for manufacturing an inverted-sidewall recessed-channel metal-oxide-semiconductor field effect transistor, comprising the steps of:

• forming an isolating layer on a silicon substrate through the LOCOS process in order to form the boundaries among the neighboring elements;
• depositing a mask oxide layer over the whole silicon substrate;
• exposing only the part of the silicon substrate for forming the channel and shallow junction of source/drain layers;
• depositing a first nitride layer over the resultant substrate;
• dry-etching the said first nitride layer so as to form a first nitride side-wall;
• forming an oxide layer being recessed into the channel by an oxidation process;
• wet-etching away the said first nitride side-wall;
• forming two doped layers for the shallow source/drain by an ion-implantation process;
• depositing a second nitride layer over the resultant substrate;
• dry-etching the said second nitride layer and the oxide layer so as to form a second nitride side-wall;
• forming a doped layer between the two doped layers for adjusting the threshold voltage and preventing the punchthrough phenomenon by an ion-implantation process;
• forming a gate oxide layer on the doped layer
• depositing a poly-silicon layer over the resultant substrate
• forming a poly-silicon gate by a lithography process and a dry-etching process;
• etching away the mask oxide layer;
• and,
• ion-implanting for thick source/drain junction.