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US 5,745,729 AGranted
Methods and apparatuses for servicing load instructions
AssigneeSun Microsystems, Inc.
InventorsDale Greenley, Leslie Kohn, Ming Yeh, Greg Williams
Life of this patent
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AssigneeSun Microsystems, Inc.
InventorsDale Greenley, Leslie Kohn, Ming Yeh, Greg Williams
Estimating the term…
A dual-ported tag array of a cache allows simultaneous access of the tag array by miss data of older LOAD instructions being returned during the same cycle that a new LOAD instruction is accessing the tag array to check for a cache hit. Because a load buffer queues LOAD instructions, the cache tags for older LOAD instructions which missed the cache return later when new LOAD instructions are accessing a tag array to check for cache hits. A method and apparatus for calculating and maintaining a hit bit in a load buffer perform the determination of whether or not a newly dispatched LOAD will hit the cache after it has been queued into the load buffer and waited for all older LOADs to be processed. A load buffer data entry includes the hit bit and all information necessary to process the LOAD instruction and calculate the hit bits for future LOAD instructions which must be buffered. A method and apparatus for servicing LOAD instructions, in which the access of the data array portion of a cache and the tag array portion are decoupled, allows the delayed access of the data array after a LOAD has been delayed in the load buffer without reaccessing the tag array. A method and apparatus allow access to the first level cache and second level cache to occur simultaneously for two separate LOADs in the load buffer.
A method of servicing load instructions in a system having a cache, a second memory system, and a load buffer, wherein the load buffer is a first-in-first-out queue which holds load instructions while the load instructions await access to either the cache or the second memory system as required, wherein the load buffer has a head of the queue position, wherein access to the cache occurs with a first latency, and wherein access to the second memory system occurs with a second latency which is greater than the first latency, the method comprising the steps of:
An apparatus for servicing load instructions in a system having a cache, a second memory system, and a load buffer, wherein the load buffer is a first-in-first-out queue which holds load instructions while the load instructions await access to either the cache or the second memory system as required, wherein the load buffer has a head of the queue position, wherein access to the cache occurs with a first latency, and wherein access to the second memory system occurs with a second latency which is greater than the first latency, the apparatus comprising:
Dependencies are inferred from the claim text.