System for distributing clocks using a delay lock loop in a programmable logic circuit

A digital delay lock loop circuit for outputting a synchronized clock locked to a reference clock signal, the digital delay lock loop circuit comprising:

• a reference clock input for receiving the reference clock signal;
• a macro phase detector coupled to the reference clock signal and a delayed feedback signal, wherein the macro phase detector outputs a macro phase error signal indicating the phase difference between the reference clock signal and the delayed feedback signal, wherein the macro phase error signal indicates phase differences of at least a first amount;
• a micro phase detector coupled to the reference clock signal and the delayed feedback signal, wherein the micro phase detector outputs a micro phase error signal indicating the phase difference between the reference clock signal and the delayed feedback signal, wherein the micro phase error signal indicates phase differences of at least a second amount wherein the second amount is smaller than the first amount;
• a macro delay selector responsive to the macro phase error signal for outputting a delayed reference clock signal;
• a micro delay selector coupled to the output of the macro delay selector, wherein in response to the micro phase error signal, the micro delay selector outputs a further delayed reference clock signal;
• and
• wherein the synchronized clock signal and said delayed feedback signal are the further delayed reference clock signal.

A digital delay lock loop circuit for outputting a synchronized clock locked to a reference clock signal, the digital delay lock loop circuit comprising:

• a reference clock input for receiving the reference clock signal;
• a feedback clock signal derived from the reference clock signal;
• a first digital phase detector coupled to the reference clock signal and the feedback clock signal, wherein the first digital phase detector determines a first phase difference between the reference clock signal and the feedback clock signal and outputs a first phase error signal at a first phase error signal output;
• a second digital phase detector coupled to the reference clock signal and the feedback clock signal, wherein the second digital phase detector determines a second phase difference between the reference clock signal and the feedback clock signal and outputs a second phase error signal at a second phase error signal output, wherein the second phase error signal is coupled to delay the feedback clock signal in response to the second phase error signal;
• a delay selector coupled to the first phase error signal and the reference clock signal for applying a delay to the reference clock signal in response to the first phase error signal, wherein the delay selector outputs a delayed reference clock signal as the feedback clock signal, wherein the synchronized clock output is coupled to the feedback clock signal, and
• a plurality of programmable delay elements, through which the synchronized clock is distributed to components of an integrated circuit, each programmable delay element is programmed to provide a uniform delay for the synchronized clock throughout the integrated circuit.

A digital delay lock loop comprising:

• a reference clock input, receiving a reference clock signal;
• a feedback clock signal derived from the reference clock signal;
• a first phase detector coupled to detect a first phase difference between the reference clock signal and the feedback clock signal;
• a second phase detector coupled to detect a second phase difference between the reference clock signal and the feedback clock signal, wherein the second phase detector detects a phase difference of an amount smaller than the first phase detector;
• a first delay selector, delaying the reference clock based on the first phase difference from the first phase detector, and generating a first delayed reference clock signal;
• and
• a second delay selector, delaying the first delayed reference clock based on the second phase difference from the second phase detector, and generating a second delayed reference clock, wherein the second delayed reference clock is coupled to the feedback clock signal, whereby the second delayed reference clock is synchronized with the reference clock signal.