Method and apparatus for upscaling an image in both horizontal and vertical directions
AssigneeParadise Electronics, Inc.
InventorAlexander J. Eglit
Life of this patent
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Abstract
An upscaler for upscaling a source image to generate a destination image without having to maintain the aspect ratio (ratio of the length of the source image to that of the width) of the source image. The source image pixel data is received at a first clock rate and the destination image is generated at a second clock rate. The second clock rate is computed such that the frame rate at which the source image is received is the same as the frame rate at which the upscaled image is generated. Because of such a clock rate, the upscaler may be implemented only a line buffer for upscaling a source image. Prior systems may require large memories such as frame buffers for achieving similar functionality.
Claims75
A method of upscaling a source image frame in both vertical and horizontal directions to generate a destination image frame, the source image frame including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image frame including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said method comprising the steps of:
- (a) receiving said plurality of source pixel data included in said source image frame using a first clock signal;
- (b) generating a second clock signal;
- (c) upscaling said source image frame in both vertical and horizontal directions to generate said plurality of destination pixel data representative of said destination image frame;
- and
- (d) providing said plurality of destination pixel data representative of said destination image frame using said second clock signal,
- wherein said second clock signal is generated to have a clock period such that the time to provide said plurality of destination pixel data is equal to a period to receive said source pixel data in said source image frame.
A circuit for upscaling a source image in both vertical and horizontal directions to generate a destination image, the source image including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said circuit comprising:
- receiving means for receiving said plurality of source pixel data included in said source image using a first clock signal;
- clock means for providing a second clock signal;
- and
- upscaling means for upscaling said source image in both vertical and horizontal directions to generate an upscaled image, wherein said upscaled image includes a number of pixels equal to a number of destination pixels in said destination image, said upscaling means providing the pixel data corresponding to said upscaled image using said second clock signal,
- wherein said second clock signal has a clock period such that the time to provide the pixel data in said upscaled image is equal to a period to receive said source pixel data in said source image.
An upscaler circuit for upscaling a source image in both vertical and horizontal directions to generate a destination image, the source image including a plurality of source scan lines, with each of said plurality of source scan lines including a plurality of source pixel data, the destination image including a plurality of destination lines, each of said plurality of destination lines including a plurality of destination pixel data, said circuit comprising:
- a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal;
- a clock signal generator for generating a destination clock signal;
- a line buffer for receiving and storing said plurality of source pixel data using said destination clock signal;
- and
- a control block for causing said plurality of source pixel data to be read from said line buffer, said control circuit causing the generation of an upscaled image which is upscaled in both vertical and horizontal directions, wherein said upscaled image includes a same number of pixel data as the number of destination image pixel data in said destination image,
- wherein said destination clock signal has a clock period such that the source frame rate is equal to said destination frame rate.
A system for displaying an image, comprising:
- receiving means for receiving a source image and providing a plurality of source pixel data representative of said source image;
- an upscaler coupled to said receiving means, said upscaler upscaling said source image in both vertical and horizontal directions to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising:
- a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal;
- a clock signal generator for generating a destination clock signal;
- a line buffer for receiving said plurality of source pixel data using said destination clock signal;
- and
- a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate;
- and
- a display screen for displaying said destination image at said destination frame rate.
A digital display device, comprising:
- receiving means for receiving a source image and providing a plurality of source pixel data representative of said source image;
- an upscaler coupled to said receiving means, said upscaler upscaling said source image in both vertical and horizontal directions to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising:
- a data synchronizer for receiving said plurality of source pixel data at a source frame rate;
- a clock signal generator for generating a destination clock signal;
- a line buffer for receiving said plurality of source pixel data using said destination clock signal;
- and
- a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock signal has a clock period such that said source frame rate is equal to said destination frame rate;
- and
- a display screen for displaying said destination image at said destination frame rate.
A computer system for displaying an image, said computer system comprising:
- a central processing unit (CPU) coupled to a bus;
- a random access memory coupled to said bus;
- receiving means coupled to said bus for receiving a source image and providing a plurality of source pixel data representative of said source image;
- an upscaler coupled to said receiving means, said upscaler upscaling said source image to generate a plurality of destination pixel data representative of a destination image, said upscaler comprising:
- a data synchronizer for receiving said plurality of source pixel data at a source frame rate using a source clock signal;
- a clock signal generator for generating a destination clock signal;
- a line buffer for receiving said plurality of source pixel data using said destination clock signal;
- and
- a control block to cause said plurality of source pixel data to be read from said line buffer, wherein said control block causes said upscaler to generate said destination image, said destination image being generated at a destination frame rate, wherein said destination clock
- signal has a clock period such that said source frame rate is equal to said destination frame rate;
- and
- a display screen for displaying said destination image at said destination frame rate.
Dependencies are inferred from the claim text.