US 5,739,579 AGranted

Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections

AssigneeIntel Corporation

InventorsChien Chiang, David B. Fraser

Life of this patent

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Abstract

A method for forming interconnections for semiconductor fabrication and semiconductor devices have such interconnections are described. A first patterned dielectric layer is formed over a semiconductor substrate and has a first opening filed with conductive material. Another patterned dielectric layer is formed over the first dielectric layer and has a second opening over at least a portion of the conductive material. The first patterned dielectric layer may serve as an etch-stop in patterning the other patterned dielectric layer. Also, a dielectric etch-stop layer may be formed over the first patterned dielectric layer and over the conductive material before the other patterned dielectric layer has been formed. This dielectric etch-stop layer may serve as an etch-stop in patterning the other patterned dielectric layer. The second opening exposes a portion of the dielectric etch-stop layer. The exposed portion of the dielectric etch-stop layer is removed. The second opening is filled with conductive material.

Claims14

Dependent claims

A semiconductor device comprising:

(a) a semiconductor substrate;
(b) a first patterned dielectric layer disposed over the semiconductor substrate, the first patterned dielectric layer having a first dielectric material and having a first opening filled with first conductive material, the first conductive material being adjacent to and in direct contact with the dielectric layer;
(c) a second patterned dielectric layer disposed over the first patterned dielectric layer, the second patterned dielectric layer having a second dielectric material and having a second opening;
and
(d) a third patterned dielectric layer disposed over the second patterned dielectric layer, the third patterned dielectric layer having a third dielectric material and having a third opening over the second opening and over at least a portion of the first conductive material, wherein the bottom of the third opening is approximately equal in width and aligned to the second opening;
wherein the second opening and the third opening are filled with second conductive material over at least a portion of the first conductive material.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/707,027Filed 10 Sep 1996 · continuation
Priority: 29 Jun 1992
Granted: 14 Apr 1998
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10W 20/077
Of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers: on sidewalls or on…
H10W 20/033
Of conductive barrier, adhesion or liner layers: in openings in dielectrics
H10W 20/039
Covering conductive structures: also covering sidewalls of the conductive structures
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches

Family

Serial905,473Parent of this continuation-in-part · filed 29 Jun 1992
Serial314,248Parent of this division · filed 28 Sep 1994
Serial430,759Parent of this continuation · filed 27 Apr 1995
US 5,612,254 AParent of this continuation-in-part
US 5,739,579 AThis patent

From the US filing history. Foreign family members aren’t listed.