Reprogrammable instruction set accelerator

A microprocessor, comprising:

• internal buses for operand and result data;
• a defined execution unit coupled to the internal buses for execution of defined instructions;
• a programmable execution unit coupled to the internal buses for execution of a programmed instruction;
• resources for accessing the programmable execution unit to define programmed instructions;
• an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit;
• an instruction state machine, responsive to condition codes, which supply instructions to the instruction register;
• and
• a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit.

A data processor comprising:

• internal buses for operand and result data;
• a defined execution unit coupled to the internal buses for execution of defined instructions;
• a programmable execution unit coupled to the internal buses for execution of a programmed instruction;
• and
• a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the data processor.

A microprocessor, comprising:

• internal buses for operand and result data;
• a defined execution unit coupled to the internal buses for execution of defined instructions;
• a programmable execution unit coupled to the internal buses for execution of a programmed instruction;
• resources for accessing the programmable execution unit to define programmed instructions;
• an instruction register which holds a current instruction for execution, and an instruction data path from the instruction register, including a decoder supplying control signals in response to instructions to the defined execution unit and to the programmable execution unit;
• an instruction state machine, responsive to condition codes, which supply instructions to the instruction register;
• a condition code register, coupled with the instruction fetching resources, and connected to receive condition codes from the defined execution unit and from the programmable execution unit;
• and
• a configuration data bus coupled to the programmable execution unit whereby the programmable execution unit is configured with data received from a source external to the microprocessor.