Method of forming conductive bumps on die for flip chip applications

A method of fabricating under bump metallization on a semiconductor substrate, comprising:

• providing a semiconductor substrate including integrated circuitry on at least one surface thereof, and at least one passivation layer having a thickness and disposed thereover;
• providing access to said semiconductor integrated circuitry for external contact by forming at least one via extending through said at least one passivation layer;
• forming a substantially conformal metal layer of a thickness substantially less than the passivation layer thickness over said at least one passivation layer with a portion of said metal layer extending into said at least one via to make electrical contact with said semiconductor integrated circuitry;
• applying an etchant-resistive material over said metal layer and into said at least one via so as to substantially fill said at least one via;
• removing said etchant-resistive material to expose said metal layer above said at least one passivation layer while having said etchant-resistive material within said at least one via;
• removing said metal layer over said at least one passivation layer except for the portion extending into said at least one via by applying an etchant to said exposed metal layer above said at least one passivation layer while protecting of said metal layer portion extending into said at least one via with said etchant-resistive material;
• and
• removing said etchant-resistive material within said at least one via.

A method of relocating a conductive element of a semiconductor substrate, comprising:

• providing a semiconductor substrate carrying integrated circuitry on at least one surface thereof, and at least one conductive element on said at least one substrate surface in communication with said circuitry, said at least one conductive element bounded by a first passivation layer over said surface;
• defining a conductive trace in contact with said at least one conductive element and extending over said first passivation layer to an alternative, laterally-offset conductive element location;
• forming a second passivation layer having a thickness over said surface and said conductive trace;
• etching a sloped-wall via through said second passivation layer extending to an upper surface of said conductive trace at said alternative conductive element location;
• forming a substantially conformal metal layer having a thickness substantially less than the second passivation layer thickness over said second passivation layer and into said sloped-wall via to make electrical contact with said conductive trace;
• and
• removing said metal layer only above said second passivation layer.