Process for fabricating a fully self-aligned soi mosfet

A process for fabricating a MOSFET device comprising the steps of:

• providing a single crystal silicon body having an insulating layer thereon, and a silicon layer overlying the insulating layer;
• forming first and second isolation regions in the silicon layer defining an active region therebetween;
• planarizing the first and second isolation regions and the active region to form a planar surface;
• forming a masking layer on the planar surface, the masking layer having an opening therein exposing a portion of the planar surface at the active region;
• forming a recess in the active region, the recess having substantially vertical sides;
• implanting the active region through the opening in the masking layer to form a first gate electrode in the single crystal silicon body;
• forming a first insulating sidewall spacer adjacent to the substantially vertical sides;
• forming a gate dielectric layer in the recess;
• depositing a gate electrode forming material to fill the recess;
• planarizing the gate electrode forming material to form a second planar surface and to define a second gate electrode overlying the gate dielectric layer;
• removing the masking layer to expose a wall surface of the gate electrode;
• forming an opening through the second gate electrode and the insulating layer;
• forming a refractory-metal plug in the opening through the second gate electrode and the insulating layer to electrically couple the first gate electrode to the second gate electrode;
• forming a second insulating sidewall spacer adjacent to the wall surface;
• forming source and drain regions in the active region on either side of the first gate electrode defining a channel region therebetween, wherein the first gate electrode is separated from the channel region by the insulating layer;
• and
• forming refractory-metal silicide regions in the source and drain regions and at an upper surface of the gate electrode.