Method of fabricating a raised source/drain MOSFET using self-aligned POCl.sub.3 for doping gate/source/drain regions

A method of fabricating a MOSFET device structure in a silicon substrate using self-aligned source for doping the gate, source and drain regions of the structure, the silicon substrate having a first conductivity type, the fabrication method comprising:

• formed spaced-apart field oxide isolation regions in the substrate to define an active device substrate region therebetween;
• forming a polysilicon gate over the active device substrate region and separated from the active device substrate region by an underlying layer of gate oxide;
• forming first and second spaced-apart lightly doped regions having a second conductivity type opposite the first conductivity type in the active device substrate region to define a substrate channel region therebetween such that the polysilicon gate is formed over the substrate channel region;
• forming oxide sidewall spacers on sidewalls of the polysilicon gate and gate oxide;
• forming a layer of polysilicon over the structure resulting from the above-recited steps;
• performing a chemical mechanical polishing (CMP) step to substantially planarize an upper surface of the structure resulting from the step of forming a layer of polysilicon to define a polysilicon gate region and first and second raised polysilicon regions formed over the first and second lightly doped regions, respectively, and formed partially over adjacent field oxide;
• forming a layer of a dopant source that includes dopant of the second conductivity type on the substantially planarized upper surface;
• thermally driving dopant from the dopant source layer into the underlying polysilicon gate region and first and second raised polysilicon regions;
• performing a rapid thermal anneal step to outdiffuse dopant from the first and second raised polysilicon regions into the underlying first and second lightly doped regions, respectively;
• and
• removing the dopant source layer.