Insulated-gate semiconductor device having a position recognizing pattern directly on the gate contact area

An insulated-gate type semiconductor device comprising:

• an insulated-gate type field effect transistor having a first conduction type semiconductor substrate serving as a drain, a second conduction type area formed in a main surface of the substrate serving as a channel, a further second conduction type area between the first conduction type area serving as a drain and the second conduction type area serving as a channel and having a lower conductivity than the second conduction type area serving as a channel to provide improved drain withstand voltage, a first conduction type area formed in a main surface of the second conduction type area serving as a source, and a semiconductor layer provided through a gate insulating film on the channel between the source and the drain serving as a gate;
• and
• a protection element for the gate of said transistor formed separately from the gate,
• wherein the gate has a contact area for coming into contract with said protection element, and a wiring pattern formed in said contact area includes a testing portion for testing a withstand voltage of the semiconductor device.

An insulated-gate type semiconductor device comprising:

• an insulated-gate type field effect transistor having a first conduction type semiconductor substrate serving as a drain, a second conduction type area formed in a main surface of the substrate serving as a channel, a first conduction type area formed in a main surface of the second conduction type area serving as a source, and a semiconductor layer provided through a gate insulating film on the channel between the source and the drain serving as a gate;
• and
• a protection element for the gate of said transistor formed separately from the gate,
• wherein the gate has a contact area for coming into contact with said protection element, and a wiring pattern formed in said contact area includes a position recognizing pattern for recognizing a position of the semiconductor device in assembling the semiconductor device and a testing portion for testing a withstand voltage of the semiconductor device.