Electrolytic method of depositing gold connectors on a printed circuit board

A method of electrodepositing metallurgy onto a feature of a printed circuit board comprising the steps of:

• a. electrolessly depositing a copper layer atop exposed surfaces of a circuitized printed circuit board;
• b. applying a layer of photoresist atop the electroless copper layer;
• c. exposing and developing the photoresist to uncover the features to be plated and surrounding peripheries;
• d. microetching the uncovered areas of the printed circuit board to form voids to the dielectric in the peripheries while leaving a copper trace to be electroplated intact whereby the remaining electroless copper forms a commoning layer;
• e. stripping the remaining photoresist to uncover the copper commoning layer;
• f. reapplying a layer of photoresist atop the partially etched copper layer;
• g. exposing and developing the photoresist to uncover only the features to be electroplated with the desired metallurgy;
• h. electroplating the metallurgy atop the features thereby forming conformally plated features with a specific metallurgy;
• i. stripping the remaining photoresist;
• and
• j. microetching the remaining electroless copper while leaving copper traces intact.

A printed circuit board having an electrical feature thereon, said feature comprising metallurgy atop a layer of electroless copper atop the board dielectric, said feature prepared by the method comprising the steps of:

• a. electrolessly depositing a copper layer atop exposed surfaces of an uncircuitized copper clad or bare dielectric printed circuit board;
• b. applying a layer of photoresist atop the electroless copper layer;
• c. exposing and developing the photoresist to uncover areas surrounding the features to be electroplated while the background Cu remains covered by photoresist;
• d. etching the uncovered areas of the printed circuit board to form voids surrounding the features to be electroplated whereby the remaining electroless copper forms a commoning layer;
• e. stripping the remaining photoresist to uncover the copper commoning layer;
• f. applying a layer of photoresist atop the partially etched copper layer;
• g. exposing and developing the photoresist to uncover the features to be plated with the desired metallurgy;
• h. electroplating the metallurgy atop the features thereby forming conformally plated features with a specific metallurgy;
• i. stripping the remaining photoresist;
• and
• j. circuitizing the uncovered layers of the printed circuit board either additively or subtractively.

A printed circuit board comprising an electrical feature thereon, said feature comprising metallurgy atop a layer of electroless copper atop a copper foil layer atop the board dielectric, said feature prepared by the method comprising the steps of:

• a. electrolessly depositing a copper layer atop exposed surfaces of an uncircuitized copper clad or bare dielectric printed circuit board;
• b. applying a layer of photoresist atop the electroless copper layer;
• c. exposing and developing the photoresist to uncover areas surrounding the features to be electroplated while the background Cu remains covered by photoresist;
• d. etching the uncovered areas of the printed circuit board to form voids surrounding the features to be electroplated whereby the remaining electroless copper forms a commoning layer;
• e. stripping the remaining photoresist to uncover the copper commoning layer;
• f. applying a layer of photoresist atop the partially etched copper layer;
• g. exposing and developing the photoresist to uncover the features to be plated with the desired metallurgy;
• h. electroplating the metallurgy atop the features thereby forming conformally plated features with a specific metallurgy;
• i. stripping the remaining photoresist;
• and
• j. circuitizing the uncovered layers of the printed circuit board either additively or subtractively.

A printed circuit board having an electrical feature thereon, said feature comprising metallurgy atop a layer of electroplated copper atop a layer of electroless copper atop a layer of copper foil atop board dielectric, said electrical feature prepared by the method comprising the steps of:

• a. electrolessly depositing a copper layer atop exposed surfaces of an uncircuitized copper clad or bare dielectric printed circuit board;
• b. applying a layer of photoresist atop the electroless copper layer;
• c. exposing and developing the photoresist to uncover areas surrounding the features to be electroplated while the background Cu remains covered by photoresist;
• d. etching the uncovered areas of the printed circuit board to form voids surrounding the features to be electroplated whereby the remaining electroless copper forms a commoning layer;
• e. stripping the remaining photoresist to uncover the copper commoning layer;
• f. applying a layer of photoresist atop the partially etched copper layer;
• g. exposing and developing the photoresist to uncover the features to be plated with the desired metallurgy;
• h. electroplating the metallurgy atop the features thereby forming conformally plated features with a specific metallurgy;
• i. stripping the remaining photoresist;
• and
• j. circuitizing the uncovered layers of the printed circuit board either additively or subtractively.

A printed circuit board having an electrical feature thereon, said feature comprising metallurgy atop a layer of electroplated copper atop a layer of electroless copper atop a layer of copper foil atop board dielectric, said electrical feature prepared by the method comprising the steps of:

• a. electrolessly depositing a copper layer atop exposed surfaces of a circuitized printed circuit board;
• b. applying a layer of photoresist atop the electroless copper layer;
• c. exposing and developing the photoresist to uncover the features to be plated and surrounding peripheries;
• d. microetching the uncovered areas of the printed circuit board to form voids to the dielectric in the peripheries while leaving a copper trace to be electroplated intact whereby the remaining electroless copper forms a commoning layer;
• e. stripping the remaining photoresist to uncover the copper commoning layer;
• f. reapplying a layer of photoresist atop the partially etched copper layer;
• g. exposing and developing the photoresist to uncover only the features to be electroplated with the desired metallurgy;
• h. electroplating the metallurgy atop the features thereby forming conformally plated features with a specific metallurgy;
• i. stripping the remaining photoresist;
• and
• j. microetching the remaining electroless copper while leaving copper traces intact.