Logic or memory element based on n-stable phase-locking of single-electron tunneling oscillation, and computer using the same
AssigneeFujitsu Limited
InventorsToshio Ohshima, Richard A. Kiehl
Life of this patent
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AssigneeFujitsu Limited
InventorsToshio Ohshima, Richard A. Kiehl
Estimating the term…
A single-electron tunneling (SET) element used as a logic or memory element includes at least one tunneling junction with a minute metal-insulator-metal sandwich structure, and a biasing power source which is connected in series to the at least one tunneling junction and whose ON/OFF operation is controlled by an external control input. SET oscillations are generated in the at least one tunneling junction and the generated oscillations are phase-locked to subharmonics of a pump signal supplied from an AC power source, to thus exhibit a plurality of stable phase states. Also, a plurality of gates, each including the SET element, are constituted in the form of a logic network to realize a predetermined logic operation in a computer. In the logic network, an input signal with a frequency half that of the pump signal is continually applied to a specified gate among the plurality of gates, while the biasing power sources of all of the gates are kept in ON state. Alternatively, when the biasing power source of the specified gate is switched ON, the biasing power sources of all of a first group of gates providing inputs to the specified gate, and the biasing power sources of all of a second group of gates providing inputs to the first group of gates, are kept in ON state.
A single-electron tunneling element excited by a pump signal supplied from an alternating current power source, comprising:
A logic circuit comprising a plurality of single-electron tunneling elements connected in the form of multiple stages and each excited by a pump signal supplied from an alternating current power source,
An input/output circuit for interfacing between an external direct current logic signal and an alternating current phase state in an internal logic circuit, said input/output circuit comprising:
A logic network constituted so as to realize a predetermined logic operation in a computer, comprising:
A logic network constituted so as to realize a predetermined logic operation in a computer, comprising:
Dependencies are inferred from the claim text.