Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance

A method for fabricating field effect transistors (FETs) having low sheet resistance gate electrodes comprising the steps of:

• providing a semiconductor substrate;
• forming shallow trench isolation regions surrounding and electrically isolating device areas;
• forming a gate oxide on said device areas by thermal oxidation;
• depositing an N.sup.+ conductively doped polysilicon layer on said substrate;
• depositing a silicon nitride layer on said polysilicon layer;
• patterning said silicon nitride layer and said polysilicon layer by photoresist masking and anisotropic etching leaving portions over said device areas to form said gate electrodes and to form electrical interconnections over said shallow trench isolation regions;
• forming lightly doped source/drain areas adjacent to said gate electrodes by ion implantation;
• depositing a conformal first insulating layer over said gate electrodes and elsewhere on said substrate;
• anisotropically etching back said first insulating layer thereby forming sidewall spacers on said gate electrodes;
• forming source/drain contact areas by ion implantation adjacent to said sidewall spacers;
• depositing a blanket first titanium (Ti) layer and annealing said substrate to form titanium silicide on said source/drain contact areas while leaving unreacted titanium on insulated surfaces of said substrate;
• stripping said unreacted first titanium from said substrate;
• depositing a blanket second insulating layer on said substrate;
• chemical/mechanically polishing said second insulating layer to said silicon nitride layer on said gate electrodes;
• removing selectively said silicon nitride layer over said gate electrodes by wet etching while leaving said second insulating layer as a self-aligning implant mask;
• implanting ions in said gate electrodes composed of said polysilicon layer thereby amorphizing the surface of said polysilicon layer, while masking said source/drain contact areas protected by said second insulating layer;
• depositing a second titanium layer and annealing to form titanium silicide on said gate electrodes while leaving on said insulating layer unreacted portions of said second titanium layer;
• stripping said unreacted second titanium on said second insulating layer, thereby completing said field effect transistors having said low sheet resistance.