US 5,729,709 A · Memory controller with burst addressing circuit

Abstract

An improved memory controller of a computer system is described. The computer system includes a microprocessor and a memory coupled to the memory controller that controls access to the memory. An interface circuit is coupled to the microprocessor for receiving a first address to access the memory. The memory includes a first memory bank and a second memory bank. A memory control circuit is coupled to the interface circuit for generating control signals to access the memory. An address generation circuit is coupled to receive the first address from the interface circuit for generating a first memory address and a second memory address in accordance with the first address to access the memory during a burst access to the memory from the microprocessor. The address generation circuit further comprises circuitry for generating and applying the first memory address sequentially to the first and second memory banks and circuitry for generating and applying the second memory address sequentially to the first and second memory banks. The second memory address is generated by inverting at least the lowest order address bit in the first memory address Access time of the burst access is minimized by using the first microprocessor memory address and generating a second memory address therefrom.

Claims44

Dependent claims

A memory controller, comprising:

(a) an input that receives a first memory address for a memory having a first memory bank and a second memory bank;
and
(b) an address and control circuit coupled to the input and the memory, wherein the address and control circuit generates a first column address strobe signal for the first memory bank, a second column address strobe signal for the second memory bank, and a sequence of memory addresses in response to the first memory address, wherein the address and control circuit alternately generates the first and second column address strobe signals to enable each of the first and second memory banks to latch the sequence of memory addresses, respectively.

A computer memory controller for generating memory control signals and a sequence of memory addresses in response to a first address received by the memory controller, comprising:

(a) an interface circuit that receives the first address having row address bits and column address bits for addressing a memory having an odd memory bank and an even memory bank;
(b) an address generation circuit coupled to the interface circuit, the address generation circuit receiving at least one of the column address bits and providing a sequence of odd column address bits and a sequence of even column address bits to the odd and even memory banks, respectively;
and
(c) a control circuit coupled to the interface circuit, the control circuit receiving at least a subset of the column address bits of the first address and providing (1) the subset of column address bits to the odd memory bank and the even memory bank and (2) an odd column address strobe signal to the odd memory bank and an even column address strobe signal to the even memory bank, the odd and even column address strobe signals being alternately asserted to enable the odd and even memory banks to latch combinations of bits output by the address generation circuit and the control circuit, wherein the row address bits and the combinations of bits collectively comprise the sequence of memory addresses, and the odd and even column address strobe signals represent the memory control signals.

1 more element

Dependencies are inferred from the claim text.

Memory controller with burst addressing circuit

Life of this patent

Memory controller with burst addressing circuit

Life of this patent

Abstract

Claims44