Data detecting circuit

Abstract

A clock extracting section generates a first clock synchronized with a reproducing signal, and a second clock with a frequency twice a frequency of the first clock. An AD converter quantizes the reproducing signal at timing of the second clock. A data classifier classifies the quantized data into two quantized data streams with a period of the first clock. Each equalizer equalizes the two quantized data streams to (1,1) and (1,2,1) partial response characteristics. Each branch metric arithmetic unit calculates a corresponding branch metric respectively. A synthesizer calculates a sum of them so as to generate a synthetic branch metric. An ACS circuit and a data decoding section Viterbi-decode data according to the synthetic branch metric. As a result, even if an SN ratio is lowered by increase in interference between codes and a noises at the time of recording at high density, an error of decoded data can be decreased.

Dependencies are inferred from the claim text.