Continuous burst edo memory device
AssigneeMicron Technology, Inc.
InventorTimothy B. Cowles
Life of this patent
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Abstract
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latch a memory address from external address lines and internally generates additional memory addresses. The integrated circuit memory can output data in a continuous stream while new rows of the memory are accessed. A method and circuit are described for outputting a burst of data stored in a first row of the memory while accessing a second row of the memory.
Claims20
A memory device comprising:
- a plurality of addressable memory elements;
- a plurality of external address inputs;
- address counter circuitry for receiving a first address on the plurality of external address inputs, and for generating a sequence of addresses in response to the first address;
- and
- output buffer circuitry adapted to drive a sequence of data from the memory device, the output buffer circuitry further adapted to continue to drive the sequence of data from the memory device while a new address is received by the address counter circuity.
A burst access memory, comprising:
- a memory array having a plurality of addressable elements arranged in rows and columns;
- row access circuitry for latching a row address and accessing a row of memory elements;
- an output buffer for outputting a sequence of data stored in a plurality of columns;
- and
- control circuitry for controlling the output buffer and the row access circuitry, wherein a new row of memory elements can be accessed without interrupting an active output sequence.
A memory device comprising:
- a plurality of addressable memory elements arranged in rows and columns;
- a plurality of external address inputs;
- address circuitry for receiving row addresses and column addresses from the plurality of external address inputs;
- counter circuitry for generating a sequence of column addresses in response to a first received column address;
- row access circuitry for accessing a row of memory elements in response to a received first row address;
- output buffer circuitry adapted to output a sequence of data from the memory device, the sequence of data being stored in the plurality of addressable memory elements having addresses corresponding to the sequence of addresses and the first row address;
- and
- control circuitry for controlling the output buffer circuitry and the access circuitry, wherein a second row of memory elements can be accessed without interrupting an active output sequence of data from the first row address.
A method of burst reading data from a memory device having a plurality of addressable memory elements arranged in rows and columns, the method comprising the steps of:
- receiving a first row address;
- receiving a first column address;
- accessing a row of memory elements having the first row address;
- generating a sequence of column addresses starting at the first column address;
- outputting data stored at the sequence of column addresses;
- receiving a second row address while outputting the data stored at the sequence of column addresses;
- and
- accessing a row of memory elements having the second row address while outputting the data stored at the sequence of column addresses.
A method of burst reading data from a memory device having a plurality of addressable memory elements arranged in rows and columns, the method comprising the steps of:
- latching a first row address in response to an active transition of a row address latch signal;
- latching a first column address in response to an active transition of a column address latch signal;
- accessing a row of memory elements having the first row address;
- reading data stored in a plurality of memory elements;
- latching the data stored in the plurality of memory elements;
- generating a sequence of column addresses starting at the first column address;
- outputting the latched data in response to active transitions of the column address latch signal;
- receiving a second row address while outputting the latched data;
- and
- accessing a row of memory elements having the second row address while outputting the latched data.
Dependencies are inferred from the claim text.