Address transition detection on a synchronous design

A circuit comprising:

• a memory array comprising a plurality of rows and a plurality of columns;
• a column address generator, operable in a burst mode and a page mode, coupled to said memory array;
• a mode select circuit coupled to said column address generator to select the burst mode or the page mode;
• an address transition detection circuit coupled to said column address generator;
• a pair of complimentary data lines coupled to said memory array;
• and
• an equilibration circuit coupled to said complimentary data lines and to said address transition detection circuit.

A circuit comprising:

• an address generator responsive to a first polarity of transitions of a control signal to provide a series of addresses;
• an address latch responsive to a second polarity of transitions of the control signal to latch each of the series of addresses;
• and
• an address transition detection circuit responsive to the latched addresses, said address transition detection circuit providing an equilibration control signal.

A method of operating a memory device having an address generation circuit, comprising steps of:

• receiving an address from a source external to the memory device;
• latching the address;
• generating a next address in the address generation circuit;
• latching the next address;
• detecting a difference between the address and the next address;
• and
• generating an equilibration signal in response to said step of detecting a difference.

A method of supplying data to a microprocessor comprising steps of:

• addressing a memory circuit with an address from the microprocessor;
• latching the address within the memory circuit;
• generating a next address within the memory circuit;
• detecting a difference between the address and the next address;
• generating an equilibration signal within the memory circuit in response to said step of detecting a difference;
• supplying data to the microprocessor from the address of the memory circuit;
• and
• supplying data to the microprocessor from the next address of the memory circuit.