Parallel-dichotomic serial sensing method for sensing multiple-level non-volatile memory cells, and sensing circuit for actuating such method

A circuit for reading a memory cell that stores one of a possible sixteen or more data values, the circuit comprising:

• an input terminal that is operable to receive a data current from said memory cell;
• an output terminal;
• three current mirrors coupled to said input terminal;
• a sequential machine having a control input, a control output, and a data output that is coupled to said output terminal, said sequential machine operable to generate at said data output a digital signal that corresponds to said stored data value, said sequential machine operable to generate a control signal at said control output;
• three comparators each having a first input terminal coupled to a corresponding one of said current mirrors, a second input terminal, and an output terminal coupled to said control input of said sequential machine;
• and
• three variable-reference-current generators each having an output coupled to said second input terminal of a corresponding one of said comparators and each having a control input coupled to said control output of said sequential machine.

Circuit for sensing multiple-level non-volatile memory cells which can take one programming level among a plurality of m=2.sup.n (n>=2) different programming levels, comprising biasing means for biasing a memory cell to be sensed in a predetermined condition, so that the memory cell sinks a cell current with a value belonging to a discrete set of m distinct cell current values, each cell current value corresponding to one of said programming levels, characterized in that it comprises a plurality of current comparators for simultaneously comparing the cell current with a plurality of reference currents generated by a plurality of variable reference current generators, and in that it further comprises a sequential machine supplied with output signals of said plurality of current comparators and controlling the variable reference current generator, the sequential machine comprising a sequential network which, starting from a predetermined initial state causing the reference current generators to generate a plurality of reference currents with value comprised between a minimum value and a maximum value of said discrete set of cell current values and dividing said discrete set of m cell current values in a plurality of sub-sets of cell current values, evolves through a succession of states each one determined by the preceding state and by the logic state of said output signals of the current comparators, each state of the sequential network causing the reference current generators to generate reference currents with values comprised between a minimum value and a maximum value of the sub-set of cell current values to which the cell current belongs and further dividing said sub-set of cell current values in a plurality of sub-sets of cell current values.