Microprocessor shifter using rotation and masking operations
AssigneeLSI Logic Corporation
InventorFrank Worrell
Life of this patent
Estimating the term…
Abstract
A shifter design which is useful in microprocessors is presented. The shifter can perform the operations of a shift right, shift left and shift right arithmetic in which the sign bit of the shifted data word is replicated into the vacated bit positions caused by the shift to the right. The shifter has a rotation count unit, a rotation unit, a mask decoder unit and a logic unit for high-speed operation and occupies a minimal amount of area in an integrated circuit.
Claims13
In a microprocessor a shifter moving input bits in a word right or left by a specified amount in response to an instruction, said shifter comprising
- a rotation count unit receiving signals specifying an amount of shift of said input bits right or left in said instruction and generating rotational control bits;
- a rotation unit receiving said input data bits and rotating said input bits by a specified amount responsive to said rotational control bits;
- a mask decode unit responsive to said rotational control bits generating masking bits;
- and
- a logic unit connected to said mask decode unit and said rotation unit combining said masking bits and rotated input bits;
- said logic unit performing a shift right by performing a logic AND of inverted masking bits and rotated input data bits, said logic unit performing a shift left by performing a logic AND of uninverted masking bits and rotated input data bits,
- said logic unit performing a shift right arithmetic with a sign bit of zero by performing a logic AND of inverted masking bits and rotated input data bits, and said logic unit performing a shift right arithmetic with a sign bit of one by performing a logic OR of masking bits and rotated input bits,
- whereby said shifter operates on said input bits in one clock cycle.
In a microprocessor a shifter moving input bits in a word right or left by a specified amount in response to an instruction, said shifter comprising
- means receiving signals specifying an amount of shift of said input bits right or left for generating rotational control bits;
- means receiving said input bits for rotating said input bits by a specified amount responsive to said rotational control bits;
- means responsive to said rotational control bits for generating masking bits;
- and
- a logic unit connected to said masking bit generating means and said rotating means to logically combine said masking bits and rotated input bits;
- said logic unit performing a shift right by performing a logic AND of inverted masking bits and rotated input data bits, said logic unit performing a shift left by performing a logic AND of uninverted masking bits and rotated input data bits,
- said logic unit performing a shift right arithmetic with a sign bit of zero by performinq a logic AND of inverted masking bits and rotated input data bits, and said logic unit performing a shift right arithmetic with a sign bit of one by performing a logic OR of masking bits and rotated input bits,
- whereby said shifter operates on said input bits in one clock cycle.
Dependencies are inferred from the claim text.