Method and circuit for reducing offset voltages for a differential input stage

A trimmable differential input stage having a first and second input and a first and second output, comprising:

• a first transistor having a drain coupled to the first output, a gate coupled to the first input, a source, and a bulk terminal;
• a second transistor having a drain coupled to the second output, a gate coupled to the second input, a source coupled to the source of the first transistor, and a bulk terminal;
• a first current source circuit having a first terminal coupled to the sources of the first transistor and the second transistor, and a second terminal coupled to a first power supply terminal for receiving a first power supply voltage;
• and
• a trim circuit coupled to said first input and said second input to provide different bias voltages selectively coupled to one of the bulk terminals of the first and second transistors for changing a threshold voltage of said one transistor to reduce an input offset voltage.

A method for reducing an input offset voltage of a differential transistor pair having a first input and a second input, comprising the steps of:

• providing each transistor of the differential transistor pair in a separate bulk region;
• providing voltage potentials by using a trim circuit coupled to said first input and said second input;
• and
• selectively biasing each separate bulk region at said different voltage potentials to reduce the input offset voltage.