Semiconductor device and power supply controller for same

A semiconductor device comprising:

• a circuit composed of MOS transistors having a threshold voltage set to a low value, a source electrode of said MOS transistors being a power supply line which is made alternatively equal to a substrate bias potential of said MOS transistors in an operating condition of the semiconductor device or to a potential higher than said substrate bias potential in an absolute potential in a standby condition of the semiconductor device;
• a first power supply line of a high potential;
• a second power supply line of a low potential;
• a third power supply line which is alternatively set to a potential equal to that of said first power supply line or to a potential lower than that of said first power supply line by some degree, and
• a fourth power supply line which is alternatively set to a potential equal to that of said second power supply line or to a potential higher than that of said second power supply line by some degree;
• wherein said circuit is a memory cell circuit which includes:
• a first inverter having a first pMOS transistor and a first nMOS transistor connected in series,
• a second inverter having a second pMOS transistor and a second nMOS transistor connected in series, said first inverter and said second inverter being connected in such a back-to-back manner that an output of each inverter is connected to an input of the other inverter,
• a third nMOS transistor connected between a first bit and the input of said first inverter and having a gate connected to a word line, and
• a fourth nMOS transistor connected between a second bit and the input of said second inverter and having a gate connected to said word line;
• a substrate bias terminal of each of said first and second pMOS transistors being connected to said first power supply line, a source of each of said first and second pMOS transistors being connected to said third power supply line, a substrate bias terminal of each of said first to fourth nMOS transistors being connected to said second power supply line, a source of each of said first and second nMOS transistors being connected to said fourth power supply line;
• the semiconductor device further comprising a control circuit including:
• said first power supply line supplied with a high potential,
• said second power supply line supplied with a low potential,
• said third power supply line connected through a first potential difference generating circuit to said first power supply line so that a potential lower than said high potential by a potential difference created by said first potential difference generating circuit is supplied to said third power supply line,
• said fourth power supply line connected through a second potential difference generating circuit to said second power supply line so that a potential higher than said low potential by a potential difference created by said second potential difference generating circuit is supplied to said fourth power supply line,
• a first switch means connected between said first and third power supply lines for short-circuiting between said first and third power supply lines when said first switch means is closed,
• a second switch means connected between said second and fourth power supply lines for short-circuiting between said second and fourth power supply lines when said second switch means is closed, and
• a control line connected to a control input of said first and second switch means to simultaneously on-off control said first and second switch means.