Semiconductor device having semiconductor elements formed in a retrograde well structure

A semiconductor device comprising:

• a semiconductor substrate having a plurality of well regions formed in a surface region of said semiconductor substrate, the plurality of well regions extending to a surface of the semiconductor substrate, the plurality of well regions being adapted to have semiconductor elements formed therein, each of the plurality of well regions having an impurity concentration profile, in a direction of increasing distance from the surface of the semiconductor substrate, in a shape of a valley, a concentration at a minimum point of said profile being greater than 5.times.10.sup.14 cm.sup.-3, and a position of said minimum point being at least 0.5 .mu.m from the surface of the semiconductor substrate, and a position of a maximum point of the profile being deeper than the position of said minimum point from the surface of the semiconductor substrate and within 1.6 .mu.m of the surface of the semiconductor substrate;
• and
• a memory including one MOSFET provided in one of the plurality of well regions, and a bipolar transistor provided in another of the plurality of well regions, the bipolar transistor having a base layer that extends from the surface of the semiconductor substrate to a depth in said another of the plurality of well regions, said depth to which the base layer extends being less than a depth of the position of the minimum point of the impurity concentration profile,
• whereby alpha-ray soft errors in the memory are decreased.

A semiconductor device comprising:

• a semiconductor substrate having a plurality of well regions formed in a surface region of the semiconductor substrate, the surface region extending to a surface of said semiconductor substrate, the plurality of well regions extending to the surface of the substrate, the plurality of well regions having an impurity concentration profile, in a direction of increasing distance from the surface of the semiconductor substrate, in a shape of a valley, a concentration at a minimum point of said profile being greater than 5.times.10.sup.14 cm.sup.-3, and a position of said minimum point being at least 0.5 .mu.m from the surface of the semiconductor substrate, and a position of a maximum point of the profile being deeper than the position of said minimum point from the surface of the semiconductor substrate and within 1.6 .mu.m of the surface of the semiconductor substrate,
• a memory including at least one MOSFET formed in at least one of said plurality of well regions, leaving a remainder of the plurality of well regions;
• and
• at least one bipolar transistor formed in at least one of the remainder of said plurality of well regions, wherein each of said at least one bipolar transistor has a base layer that extends from the surface of the semiconductor substrate to a depth in a respective well region of the remainder of said plurality of well regions, and wherein said depth to which the base layer extends is less than a depth of the position of the minimum point of the impurity concentration profile,
• whereby alpha-ray soft errors in the memory are decreased.