Fault-tolerant boot strap mechanism for a multiprocessor system

A method of booting a multiprocessor (MP) computing system which includes a plurality of processors coupled to a system bus and to a dedicated bus, the method comprising the steps of:

• (a) optionally executing a self-test routine by each of the plurality of processors;
• (b) sending a boot message on the dedicated bus by each of the plurality of processors, the boot message containing an identification (ID) of the processor;
• (c) comparing by an individual processor the ID of the boot message on the dedicated bus with the individual processor's ID;
• if a match exists, the individual processor is a bootstrap processor (BSP);
• otherwise the individual processor is a non-BSP;
• (d) issuing a final boot message on the dedicated bus by the BSP;
• (e) receiving the final boot message by the BSP;
• (f) fetching code from a memory by the BSP via the system bus;
• (g) executing the code to start a reset sequence;
• and
• (h) issuing a start message on the dedicated bus to the non-BSPs.

A method of starting a computer system which includes first and second processors coupled to an external bus and to a dedicated bus, the second processor comprising an upgraded version of the first processor, the method comprising the steps of:

• (a) optionally executing a self-test routing by the first and second processors;
• (b) sending first and second boot messages by the first and second processors, respectively, each of the boot messages containing an identification (ID) of the respective processors:
• if the first boot message completes first, then
• (c) issuing a final boot message on the dedicated bus by the first processor;
• (d) shutting down the first processor's core after the second boot message completes;
• (e) receiving by the second processor the final boot message issued in step (c);
• else, if the second boot message completes first, then
• (f) shutting down the first processor's core;
• (g) issuing a final boot message on the dedicated bus by the second processor;
• (h) receiving by the second processor the final boot message issued in step (g);
• and then
• (i) fetching code from a memory by the BSP via the external bus;
• (j) executing the code to start a reset sequence.

A multiprocessor (MP) computing system comprising:

• a system bus;
• a non-volatile memory coupled to the system bus storing a basic/output system (BIOS) reset sequence;
• a serial bus having an arbitration mechanism;
• a plurality of processors coupled to the system bus and to the serial bus, each processor including message handling circuitry that receives and sends messages on the serial bus;
• wherein upon power-up or reset of the MP system the message handling circuitry being operable to execute a protocol in which each processor first sends a boot message on the serial bus, the boot message having a vector field which contains an identification (ID) of the processor;
• thereafter the message handling circuitry of an individual processor monitoring the serial bus to identify if the ID of the boot message currently on the serial bus matches the ID of the individual processor;
• if so, the individual processor is designated a bootstrap processor (BSP);
• otherwise, the individual processor is designated a non-BSP;
• the BSP issuing a final boot message on the serial bus which places the non-BSPs in a halt state, after the BSP receives the final boot message, the BSP fetches the BIOS reset sequence via the system bus,
• following execution of the BIOS reset sequence the BSP sending a start message on the serial bus to the non-BSPs.