Semiconductor memory device with reduced chip area

A semiconductor memory device comprising:

• a memory cell block composed of a plurality of memory cells arranged in a matrix;
• two pairs of data lines provided for said memory cell block and respectively corresponding to every two columns of memory cells;
• a plurality of word lines each of which is connected to a row of memory cells of said memory cell block;
• a row decoder circuit provided for said memory cell block, and selectively activated in accordance with an address to activate one of said plurality of word lines and said two pair of data lines;
• a pair of digit lines provided for each column of memory cells of said memory cell block;
• a sense amplifier provided for each column of memory cells, for amplifying differential data signals on said digit lines;
• a column decoder circuit provided for said memory cell block, for selectively activating two of a plurality of columns of memory cells in accordance with said address and selectively setting the two activated columns of memory cells to one of a read mode and a write mode in a read/write control signal;
• a read data transfer circuit provided for each column of memory cells, for respectively transferring differential read data signals on said digit lines to a corresponding one of said two pairs of digit lines in said read mode when said column of memory cells is activated by said column decoder circuit, said differential read data signals corresponding to data read out from one memory cell of said activated column of memory cells connected to the activated word line and amplified by said sense amplifiers;
• and
• a write data transfer circuit provided for each column of memory cells, for respectively transferring differential write data signals on said data lines to the corresponding one of said two pairs of digit lines in said write mode when said column of memory cells is activated by said column decoder circuit, data corresponding to said differential write data signals being written in one memory cell of said activated columns of memory cells connected to the activated word line.

A semiconductor memory device comprising:

• a pair of data lines on which information for a memory cell is transferred;
• a sense amplifier for amplifying said information;
• a pair of first transistors receiving said information amplified by said sense amplifier at control terminals;
• a pair of second transistors provided between signal terminals of said pair of first transistors and said pair of data lines, for outputting said amplified information to said pair of data lines in response to a data read column select signal supplied to control terminals of said pair of second transistors;
• and
• a pair of third transistors provided between said pair of data lines and said sense amplifier, for supplying said information on said pair of data lines to said sense amplifier in response to a data write column select signal supplied to control terminals of said pair of third transistors.