Logic block structure optimized for sum generation
AssigneeXilinx, Inc.
InventorsJonathan S. Rose, Trevor J. Bauer
Life of this patent
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Abstract
The present invention is part of a Field Programmable Gate Array logic block which performs arithmetic functions as well as logic functions. The novel structure includes a small amount of extra hardware which can implement the XOR function as well as several other useful functions. With the invention, one-bit adders can be generated using only a single lookup table, a carry multiplexer, and the extra hardware. N-bit adders can be implemented with N lookup tables. Multipliers, adders, counters, loadable synchronous set-reset counters and many other common functions are all more efficiently implemented with the invention.
Claims3
A field programmable gate array (FPGA) logic block structure comprising:
- a first multiplexer having at least two data inputs and at least one control input;
- a second multiplexer having at least two data inputs and at least one control input, said second multiplexer providing a first data input to said first multiplexer;
- a first lookup table having a plurality of inputs, said first lookup table providing true and complement output signals, one as a second data input to said first multiplexer and one as a first data input to said second multiplexer;
- a second lookup table having a plurality of inputs, said second lookup table providing a second data input to said second multiplexer;
- and
- a plurality of lines accessible from a general interconnect structure of an FPGA, one of said lines providing a control input to said first multiplexer, and other of said lines providing said inputs to said first and second lookup tables.
Dependencies are inferred from the claim text.