Semiconductor device having first and second semiconductor chips with a gap therebetween, a die stage in the gap and associated lead frames disposed in a package, the lead frames providing electrical connections from the chips to an exterior of the packag

A semiconductor device, comprising:

• a package enclosing therein first and second semiconductor chips having respective, opposed main surfaces disposed in parallel relationship, spaced in a first direction and defining a gap therebetween, a selected main surface of each of the first and second semiconductor chips having circuitry thereon and the first and second semiconductor chips further having respective, first and second parallel sides spaced apart in a second direction, perpendicular to the first direction;
• first and second lead frames, each lead frame having respective inner and outer ends, the inner ends of the first lead frames being disposed, within the package, adjacent the respective first sides of the first and second semiconductor chips and the inner ends of the second lead frames being disposed adjacent the respective second sides of the first and second semiconductor chips and the first and second lead frames extending from the respective inner ends thereof to the respective outer ends thereof, the outer ends being disposed exteriorally of the package;
• a die stage disposed in the gap between the first and second semiconductor chips and having opposed main surfaces parallel to and facing, respectively, the gap defining main surfaces of the first and second semiconductor chips;
• sets of TAB leads respectively associated with, and connected to, the first and second lead frames and extending therefrom, in the second direction toward the first and second semiconductor chips, each set of TAB leads comprising first TAB leads making electrical connections to the electrical circuitry on the selected main surface of the first semiconductor chip and second TAB leads, spaced in the first direction from the first TAB leads and making electrical connections to the electrical circuitry on the selected main surface of the second semiconductor chip, the selected main surface of at least one of the first and second semiconductor chips being the gap defining main surface thereof;
• and
• electrical insulation disposed between the gap defining selected main surface of the at least one of the first and second semiconductor chips and the respective, opposed main surface of the die stage and electrically insulating the inner ends of the TAB leads electrically connected to the circuitry thereon from the respective, facing main surface of the die stage.