Multicomputer memory access architecture

A scalable multicomputer comprising

• (a) a plurality of processing nodes, each having memory means for storing memory address-accessible digital signals, each of said processing nodes having associated processing means for executing a memory access instruction for generating an access request for access to a digital signal stored in at least one of said memory means, the access request including a memory address associated with that digital signal,
• (b) at least one processing node including
• mapping means for mapping selected addresses contained in access requests generated by the associated processing means to addresses in the memory means of that processing nodes and for mapping other selected addresses contained in access requests generated by the associated processing means to addresses in the memory means of another processing node, whereby each processing node can directly access the memory means of another processing node by executing memory access instructions of the type that it uses to access its own memory means,
• a crossbar interface, coupled to a port of a scalable crossbar, said crossbar interface including routing means responsive to selected access requests including those other selected addresses for generating a routing signal representative of a succession of crossbar ports between the associated processing node and a processing node where the requested digital signal is stored, and for transmitting said routing signal to the crossbar port to which said crossbar interface is coupled,
• (c) the scalable crossbar for transferring a request and any digital signals accessed thereby between the processing node that generated the request and the processing node where the digital signal is stored, the scalable crossbar comprising a plurality of crossbar elements, each crossbar element having
• a plurality of ports (i) at least one of which is coupled to a port of another crossbar element, (ii) another of which is coupled to any of a port of another crossbar element and a crossbar interface of a processing node,
• decoding means responsive to said routing signal for establishing an internal path through the crossbar element for routing the request and any digital signals accessed thereby between selected ports thereof,
• (d) said routing means including means for generating a routing signal including a broadcast signal designating a broadcast mode of communication, and
• at least one of said crossbar elements including means responsive to said broadcast signal for establishing multiple communications paths therethrough.

A scalable multicomputer comprising

• (a) a plurality of processing nodes, each having memory means for storing memory address-accessible digital signals, each of said processing nodes having associated processing means for executing a memory access instruction for generating an access request for access to a digital signal stored in at least one of said memory means, the access request including a memory address associated with that digital signal,
• (b) at least one processing node including
• mapping means for mapping selected addresses contained in access requests generated by the associated processing means to addresses in the memory means of that processing nodes and for mapping other selected addresses contained in access requests generated by the associated processing means to addresses in the memory means of another processing node, whereby each processing node can directly access the memory means of another processing node by executing memory access instructions of the type that it uses to access its own memory means,
• a crossbar interface, coupled to a port of a scalable crossbar, said crossbar interface including routing means responsive to selected access requests including those other selected addresses for generating a routing signal representative of a succession of crossbar ports between the associated processing node and a processing node where the requested digital signal is stored, and for transmitting said routing signal to the crossbar port to which said crossbar interface is coupled,
• (c) the scalable crossbar for transferring a request and any digital signals accessed thereby between the processing node that generated the request and the processing node where the digital signal is stored, the scalable crossbar comprising a plurality of crossbar elements, each crossbar element having
• a plurality of ports (i) at least one of which is coupled to a port of another crossbar element, (ii) another of which is coupled to any of a port of another crossbar element and a crossbar interface of a processing node,
• decoding means responsive to said routing signal for establishing an internal path through the crossbar element for routing the request and any digital signals accessed thereby between selected ports thereof,
• (d) said routing means including means for generating a routing signal that includes a priority signal designating a relative priority thereof, and
• at least one of said crossbar elements including means responsive to said priority signal for establishing and disestablishing internal paths therethrough in accord with said priority signal.