Low threshold voltage, high performance junction transistor
AssigneeSun Microsystems, Inc.
InventorsJames B. Burr, Michael P. Brassington
Life of this patent
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Abstract
Low threshold voltage MOS devices having buried electrodes are disclosed herein. Such devices have source and drain regions which include tip regions and plug regions. The buried electrodes have bottom boundaries located above the bottoms of the plug regions. The buried electrode has the same conductivity type as the device's bulk (albeit at a higher dopant concentration) and, of course, the opposite conductivity type as the device's source and drain. The exact dopant concentrations and locations of the buried electrodes should be provided such that punch through is avoided in MOS devices.
Claims27
A MOS device on a semiconductor substrate which has an upper surface, the MOS device comprising:
- a bulk region in said semiconductor substrate extending downward from said upper surface and having an average concentration of dopant of a first conductivity type;
- source and drain regions of a second conductivity type extending from the semiconductor substrate surface into said bulk region by a predefined distance;
- a channel region of the first conductivity type located between the source and drain regions;
- a buried electrode region of the first conductivity type within the bulk region having an upper boundary located at or above the predefined distance, said buried electrode region having a dopant concentration that is greater than the average dopant concentration in the bulk region;
- and
- a gate positioned over the channel region, wherein the MOS device has a gate threshold voltage of between about .+-.150 mV, and wherein the buried electrode dopant concentration is at least about 10 times greater than an average dopant concentration in the bulk region, whereby the likelihood of punch through is diminished.
A MOS device on a semiconductor substrate which has an upper surface, the MOS device comprising:
- a retrograde well region in said semiconductor substrate extending downward from said upper surface and having a graded concentration of dopant of the first conductivity type such that the dopant concentration is greater near the bottom of the well region;
- source and drain regions of a second conductivity type which extend from the semiconductor substrate surface into the said retrograde well region;
- a channel region of the first conductivity type located between the source and drain regions;
- and
- a gate positioned over the channel region, wherein the MOS device has a gate threshold voltage of between about .+-.150 mV, and wherein the dopant concentration proximate the bottom of the retrograde well is at least about 10 times greater than an average dopant concentration in the channel region, whereby the likelihood of punch through is diminished.
A MOS device on a semiconductor substrate which has an upper surface, the MOS device comprising:
- a bulk region in said semiconductor substrate extending downward from said upper surface and having an average concentration of dopant of a first conductivity type;
- source and drain regions of a second conductivity type extending from the semiconductor substrate surface into said bulk region by a predefined distance;
- a channel region of the first conductivity type located between the source and drain regions;
- a buried electrode region of the first conductivity type within the bulk region having an upper boundary disposed above the predefined distance, said buried electrode having a dopant concentration that is greater than the average dopant concentration in the bulk region;
- and
- a gate positioned over the channel region, wherein the MOS device has a gate threshold voltage of between about .+-.150 mV, and wherein the buried electrode dopant concentration is at least about 10 times greater than an average dopant concentration in the bulk region, whereby the likelihood of punch through is diminished and thereby allowing the MOS device to be tuned such that an applied back bias of 1 volt will shift the device's threshold voltage by between about 50 and 300 millivolts.
Dependencies are inferred from the claim text.