Advanced parallel array processor (APAP)

A multi-processor memory system comprising:

• on a chip a plurality of processing elements with a network interface, said processing elements of said chip being intercoupled by an internal communication network for passing information between processing elements on the chip, and having a broadcast port for external communication from the chip, said processing elements on the chip have their own memory and they are coupled in a network as a torus, said system having a plurality of chips which are coupled chip to chip to form a parallel array of multiple nodes of chips, each node having a broadcast and control interface for communications between processing elements on a chip and between nodes.

A computer system, comprising a plurality of chips which are coupled to form a parallel array of multiple nodes, each node having a broadcast and control interface for communications between processing elements on a chip and between nodes, said nodes being coupled by a network which is hypercube, selection means for selection of coupling paths to nodes in said modified hypercube network of nodes to change a path of coupled nodes in the network for the purpose of loading a node in parallel;

• wherein the computer system provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.

A parallel array computer system, comprising:

• a plurality of processing elements each having accessible memory and organized as cluster of processing elements, each of said processing elements of a cluster having a fast I/O tri-state driver;
• wherein the parallel array computer system provides a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein each dedicated local memory is independently accessible by the respectively coupled processor in both SIMD and MIMD modes exclusive of access by another processor.