Nano-structure memory device

A memory cell for storing k electrons or holes, where k is an integer zero or greater, indicative of data comprising:

• a semiconductor channel,
• a first insulator layer formed on said semiconductor channel,
• a first nanocrystal formed on said first insulator layer, said first nanocrystal electrically floating and capacitively coupled to said semiconductor channel with Coulomb blockade energy, greater than the thermal voltage;
• a second insulator layer over said first nanocrystal,
• a second nanocrystal formed on said second insulator layer, said second nanocrystal electrically floating and capacitively coupled to said semiconductor channel with Coulomb blockade energy, greater than the thermal voltage;
• a third insulator layer over said second nanocrystal, and
• a gate electrode formed on said third insulator layer.

A memory comprising:

• a plurality of storage devices for storing electrons or holes, each said device having a gate electrode, source region, drain region, channel, a barrier insulator layer above said channel, a nanocrystal above said barrier insulator layer, a control insulator layer above said nanocrystal, and said gate electrode on said control insulator layer,
• said plurality of storage devices arranged in rows and columns,
• said gate electrode of each storage device in each respective row coupled together and to a word line decoder,
• said source region of each storage device in each respective column coupled together and to a bitline decoder, and
• said drain region of each storage device in each respective column coupled together and to an input of a sense amplifier for sensing the data on its input.

A memory comprising:

• a plurality of storage devices for storing electrons or holes, each said device having a gate electrode, source region, drain region, channel, a barrier insulator layer above said channel, a nanocrystal above said barrier insulator layer, a control insulator layer above said nanocrystal, and said gate electrode on said control insulator layer,
• said plurality of storage devices arranged in rows and columns,
• said gate electrode of each storage device in each respective row coupled together and to a word line decoder,
• said source region of each storage device in each respective column coupled together and to an input of a column decoder,
• said drain region of each storage device in each respective column coupled together and to an input of said column decoder, and
• an amplifier coupled to said column decoder for sensing data.