Method of making a high voltage planar edge termination structure

A method for forming a semiconductor structure having an edge termination feature comprising the steps of:

• providing a semiconductor layer of a first conductivity type and having an edge;
• forming a first doped region of a second conductivity type in the semiconductor layer to form a pn junction together with the semiconductor layer, wherein the first doped region has an impurity concentration higher than that of the semiconductor layer;
• forming a second doped region of the second conductivity type in the semiconductor layer, wherein the second doped region is coupled with the first doped region, and wherein the second doped region has an impurity concentration lower than that of the first doped region, and wherein the second doped region has a substantially uniform depth;
• forming an electrically insulating layer disposed on the semiconductor layer so as to extend over the second doped region, and wherein the electrically insulating layer varies in thickness such that the electrically insulating layer is thicker towards the edge of semiconductor layer;
• and
• forming a polysilicon layer disposed over the electrically insulating layer and over at least a portion of the second doped region, wherein the polysilicon layer has a coil-shaped configuration that extends over the varied thickness of the electrically insulating layer and is electrically coupled at an inner portion to the first doped region and electrically coupled at an outer portion to the semiconductor layer, and wherein the polysilicon layer does not make direct contact to the second doped region.

A method for forming a semiconductor device comprising the steps of:

• providing a semiconductor substrate having a first conductivity type and an edge;
• forming a first electrically insulating layer over the semiconductor substrate;
• selectively patterning the first electrically insulating layer to expose a first portion of the semiconductor substrate;
• forming a first doped region of a second conductivity type in the first portion of the semiconductor substrate and extending to a first depth;
• selectively patterning the first electrically insulating layer to expose a second portion of the semiconductor substrate while leaving a portion of the first electrically insulating layer near the edge;
• forming a second doped region of the second conductivity type in the second portion of the semiconductor substrate, wherein the second doped region is coupled to the first doped region, and wherein the second doped region has a second depth less than the first depth;
• forming a second electrically insulating layer over the second doped region, wherein the second insulating layer is thinner than the first electrically insulating layer;
• and
• forming a conductive layer with a coil-shaped configuration over the first and second electrically insulating layers, wherein the conductive layer is coupled to the first doped region and the semiconductor substrate.