# US 5,710,938 A · Data processing array in which sub-arrays are established and run independently > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,710,938 A - Document ID: US5710938A - Status: Granted - Kind: A - Application number: 08/504,303 - Filed: 1995-07-19 - Granted: 1998-01-20 - Earliest claimed: 1995-07-19 - Assignees: Unisys Corporation - Inventors: Curtis Wayne Dahl; Daniel Allen Neuss; Mark Steven Collett; Mark Elliot Bsharah - Web page: https://patentgrep.com/patent/US5710938A ## CPC - G06F 15/8023: {Two dimensional arrays, e.g. mesh, torus} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing array is partitioned by electronic control signals into multiple sub-arrays which are established and operate independently of each other. In the preferred embodiment, an operator's console is provided for manually selecting the data processing nodes that are in each sub-array, and a control module is coupled by control channels between the console and the data processing nodes. These control channels carry the control signals directly to the data processing nodes without utilizing the input/output channels which are intercoupled to form the array. One portion of these control signals prevent each node in a sub-array from sending messages on the input/output channels to any node in another sub-array; and another portion of the control signals select a node in each sub-array as a boot node from which a separate operating system and user programs are loaded without utilizing the input/output channels. ## Claims ### Claim 1 A data processing system which is comprised of: a plurality of message routing circuits that have input/output channels which are intercoupled to form an array, and a corresponding plurality of data processing nodes each of which has an input/output channel to a respective message routing circuit; each data processing node being adapted to send messages which address other data processing nodes, and each message routing circuit being adapted to pass said messages on said input/output channels to the addresses data processing nodes; wherein, said data processing system further includes an operator console for manually selecting a subset of said data processing nodes that are to comprise a sub-array, a control module connected to said operator console by a first control channel for receiving commands from said console which define said sub-array; a second control channel connected directly to every data processing node and a third control channel connected directly to every message routing circuit which carry control signals from said control module that cause said sub-array to form without any of said messages being passed on any of said input/output channels. ### Claim 2 (depends on 1) A data processing system according to claim 1 wherein said control module sends said control signals directly to said data processing nodes that prevent each node in one sub-array from sending messages to any node in another sub-array. ### Claim 3 (depends on 1) A data processing system according to claim 1 wherein said control module sends control signals directly to said message routing circuits that prevent the message routing circuit in each sub-array from passing messages to another sub-array. ### Claim 4 (depends on 1) A data processing system according to claim 1 wherein said control module sends control signals directly to said data processing nodes that select one node in each sub-array as a boot node which loads a separate operating system into each sub-array via a peripheral device which is coupled directly to said boot node. ### Claim 5 (depends on 1) A data processing system according to claim 1 wherein each data processing node within a particular sub-array stores control signals which define an address for the nodes within its particular sub-array, which is independent of where the sub-array is located within said array. ### Claim 6 (depends on 1) A data processing system according to claim 1 wherein each data processing node within a particular sub-array stores control signals which define address limits for messages from that node with said address limits being independent of where the sub-array is located within said array. ### Claim 7 (depends on 1) A data processing system according to claim 1 wherein the data processing nodes in each sub-array stores a table which correlates an address for each data processing node in the sub-array to processes which those data processing nodes perform. ### Claim 8 (depends on 1) A data processing system according to claim 1 wherein said message routing circuits within each sub-array set an error indicator if any message is received for another sub-array, and a control module is coupled to said message routing circuits for reading said error indicator. ### Claim 9 (depends on 1) A data processing system according to claim 1 wherein said message routing circuits within each sub-array have their input/output channels intercoupled in rows and columns that lie in a single plane. ### Claim 10 (depends on 1) A data processing system according to claim 1 wherein said message routing circuits within each sub-array have their input/output channels intercoupled in rows and columns that lie in multiple parallel planes. ### Claim 11 (depends on 2) A data processing system according to claim 2 wherein said control module also sends control signals directly to said data processing nodes that select one node in each sub-array as a boot node which loads a separate operating system into each sub-array via a peripheral device which is coupled directly to said boot node. ### Claim 12 (depends on 11) A data processing system according to claim 11 wherein said control module also sends control signals directly to said message routing circuits that prevent the message routing circuit in each sub-array from passing messages to another sub-array.