# US 5,710,935 A · Advanced parallel array processor (APAP)

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- Number: US 5,710,935 A
- Document ID: US5710935A
- Status: Granted
- Kind: A
- Application number: 08/466,462
- Filed: 1995-06-06
- Granted: 1998-01-20
- Earliest claimed: 1990-11-13
- Assignees: International Business Machines Corporation
- Inventors: Thomas Norman Barker; Clive Allan Collins; Michael Charles Dapp; James Warren Dieffenderfer; Donald George Grice; Peter Michael Kogge; David Christopher Kuchinski; Billy Jack Knowles; Donald Michael Lesmeister; Richard Ernest Miles; Richard Edward Nier; Eric Eugene Retter; Robert Reist Richardson; David Bruce Rolfe; Nicholas Jerome Schoonover; Vincent John Smoral; James Robert Stupp; Paul Amba Wilkinson
- Web page: https://patentgrep.com/patent/US5710935A

## CPC

- G06F 7/483: Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)}
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30167: {of immediate specifier, e.g. constants}
- G06F 9/30189: {according to execution mode, e.g. mode flag}
- G06F 9/3834: {Maintaining memory consistency}
- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3885: {using a plurality of independent parallel functional units}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/3889: {controlled by multiple instructions, e.g. MIMD, decoupled access or execute}
- G06F 9/3891: {organised in groups of units sharing resources, e.g. clusters}
- G06F 15/17337: {Direct connection machines, e.g. completely connected computers, point to point communication networks (coupling between buses G06F13/4004)}
- G06F 15/17343: {wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture (reconfigurable processors arrays G06F15/7867)}
- G06F 15/17368: {non hierarchical topologies}
- G06F 15/17381: {Two dimensional, e.g. mesh, torus}
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 15/8015: {One dimensional arrays, e.g. rings, linear arrays, buses}
- G06F 15/803: {Three-dimensional arrays or hypercubes}
- G06F 15/8092: {Array of vector units}
- F02B 2075/027: {four}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- F02B: INTERNAL-COMBUSTION PISTON ENGINES; COMBUSTION ENGINES IN GENERAL (gas-turbine plants F02C; hot-gas or combustion-product positive-displacement engine plants F02G)

## Abstract

A computer system having a plurality of processors and memory including a plurality of scalable nodes having multiple like processor memory elements. Each of the processor memory elements has a plurality of communication paths for communication within a node to other like processor memory elements within the node. Each of the processor memory elements also has a communication path for communication external to the node to another like scalable node of the computer system.

## Claims

### Claim 1

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication from the chip, said chip having a single broadcast and control interface for processor-memory elements on said chip, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a pluralitv of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 2

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication from the chip, said chip having a single broadcast and control interface for processor-memory elements on said chip, wherein the chips are coupled in a network as a mesh, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 3

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication from the chip, wherein the chips are coupled in a network as a torus, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memorv element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 4

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip can broadcast in one clock cycle to all processor-memory elements on the chip, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a pME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 5

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip have a store and forward mode, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node. said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 6

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip have a store and forward mode for passing message, means examining a broadcast message in a processor-memory element was to whether it is a store and forward item, and if it is, local DMA controls enter the message and store the message in memory to free up the processor-memory element for other execution, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 7

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, wherein the processor-memory elements on the chip have a store and forward mode for passing message, means examining a broadcast message in a processor-memory element was to whether it is a store and forward item, and if it is not directed to the particular processor-memory elements the message is switched to an internal output port of the processor-memory element, and wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 8

A multi-processor memory element comprising: on a chip a plurality of processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for communication, means for processing operands of 1 to N words with a length defined by an instruction which enables a processor-memory element to perform operations on a single word length which may be a multiple of the processor-memory element word length, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 9

A processor memory element comprising: on a chip one or more processor-memory elements with a network interface, said processor-memory elements of said chip being intercoupled by an internal communication network for passing information between processor-memory elements on the chip, and having a broadcast port for external communication, each processor-memory element having an instruction set architecture which includes an instruction for a processor-memory element status switch to control dynamic switch of modes between MIMD and SIMD, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.

### Claim 10

A computer system, comprising: a plurality of processor-memory elements each having accessible memory, means for initiating the operation of the processor-memory elements in SIMD mode, an external controller having means for broadcasting code to said processor-memory elements upon initiation of the system, means for initiating a subsequent MIMD mode switch in said processor-memory elements by an external command causing the processor-memory elements which receive the command to begin execution in MIMD switched mode, wherein a plurality of multi-processor memory elements comprise a multi-processor memory system including a PME architecture multi-processor memory element on a single semiconductor substrate which functions as a system node, said multi-processor memory element including a plurality of processing memory elements, and means on said substrate for distributing interconnection and controls within the multi-processor memory system node enabling the system to perform SIMD/MIMD functions as a multi-processor memory system, wherein dedicated local memories are independently accessible by respectively coupled processors in both SIMD and MIMD modes exclusive of access by another processor.