# US 5,710,906 A · Predictive snooping of cache memory for master-initiated accesses > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,710,906 A - Document ID: US5710906A - Status: Granted - Kind: A - Application number: 08/499,610 - Filed: 1995-07-07 - Granted: 1998-01-20 - Earliest claimed: 1995-07-07 - Assignees: OPTi Inc. - Inventors: Subir Ghosh; Hsu-Tien Tung - Web page: https://patentgrep.com/patent/US5710906A ## CPC - G06F 12/0835: {for main memory peripheral accesses (e.g. I/O or DMA)} - G06F 12/0862: with prefetch - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract When a PCI-bus controller receives a request from a PCI-bus master to transfer data with an address in secondary memory, the controller performs an initial inquire cycle and withholds TRDY# to the PCI-bus master until any write-back cycle completes. The controller then allows the burst access to take place between secondary memory and the PCI-bus master, and simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line. In this manner, if the PCI burst continues past the cache line boundary, the new inquire cycle will already have taken place, or will already be in progress, thereby allowing the burst to proceed with, at most, a short delay. Predictive snoop cycles are not performed if the first transfer of a PCI-bus master access would be the last transfer before a cache line boundary is reached. ## Claims ### Claim 1 A method for transferring a plurality of data units between a bus master and a respective plurality of memory locations at sequential memory location addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising the steps of: sequentially transferring data units between said bus master and said secondary memory beginning at a starting memory location address in said secondary memory address space and continuing beyond an l-byte boundary of said secondary memory address space, said sequentially transferred data units including a last data unit before said l-byte boundary and a first data unit beyond said l-byte boundary; and initiating a next-line inquiry, prior to completion of the transfer of the last data unit before said l-byte boundary, to determine whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being a line of said secondary memory which includes said first data unit beyond said l-byte boundary. ### Claim 2 (depends on 1) A method according to claim 1, further comprising, if said next-line inquiry determines that said N+1'th l-byte line of secondary memory is cached in a modified state in said first cache memory, the steps of: stopping said step of sequentially transferring data units at said l-byte boundary; and continuing said step of sequentially transferring data units beyond said l-byte boundary after a write-back of said N+1'th l-byte line from said first cache memory to said secondary memory. ### Claim 3 (depends on 1) A method according to claim 1, wherein said secondary memory includes a tertiary memory and further includes a second cache memory which caches memory locations of said tertiary memory for said host processing unit and said first cache memory in combination. ### Claim 4 (depends on 1) A method according to claim 1, further comprising, prior to said step of sequentially transferring, the steps of: receiving an indication of said starting memory location address from said bus master; and initiating a first inquiry of whether an N'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N'th l-byte line being a line of said secondary memory which includes the data unit of said starting memory location address, said first inquiry returning negatively if the N'th l-byte line is not cached in the modified state and issuing a write-back cycle if the N'th l-byte line is cached in a modified state, wherein said next-line inquiry is initiated at a time responsive to the time that said first inquiry returns negatively or that said write-back cycle completes, whichever occurs in response to said first inquiry, and wherein said time that said next-line inquiry is initiated is not responsive to the time of said transfer of said last data unit before said l-byte boundary. ### Claim 5 (depends on 1) A method according to claim 1, wherein said starting memory location address is not the address of the last data unit before said l-byte boundary, further for transferring a second plurality of data units between said bus master and a second respective plurality of memory locations at sequential memory location addresses in said secondary memory address space, beginning with a second starting memory location address which is the address of the highest data unit in an M'th l-byte line of said secondary memory, further comprising the steps of: transferring said highest data unit between said bus master and said secondary memory; initiating a second inquiry to determine whether the M+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said second inquiry returning negatively if the M+1'th l-byte line is not cached in the modified state and issuing a write-back cycle if the M+1'th l-byte line is cached in a modified state; and sequentially transferring data units between said bus master and said secondary memory beginning at the first memory location address in said M+1'th l-byte line only after said second inquiry returns negatively or said write-back cycle completes, whichever occurs in response to said second inquiry. ### Claim 6 (depends on 5) A method according to claim 5, wherein said step of transferring said highest data unit occurs after said step of initiating a second inquiry. ### Claim 7 (depends on 1) A method according to claim 1, wherein said bus master is a PCI bus master, wherein said first cache memory includes an instruction cache and a data cache, and wherein said host processing unit and said first cache memory are fabricated on a single CPU chip. ### Claim 8 (depends on 1) A method according to claim 1, wherein said next-line inquiry takes place concurrently with at least one of the data unit transfers in said step of sequentially transferring. ### Claim 9 A method for transferring data between a bus master and a plurality of memory locations at respective addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising the steps of: sequentially transferring at least three data units between said bus master and said secondary memory beginning at a first starting memory location address in said secondary memory address space and continuing sequentially beyond an l-byte boundary of said secondary memory address space; and prior to completion of the transfer of the first data unit beyond said l-byte boundary, determining whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being the line of said secondary memory which includes said first data unit beyond said l-byte boundary, all of said transfers of data units in said step of sequentially transferring, occurring at a constant rate. ### Claim 10 A method for use with a host processing subsystem, a bus master and memory locations addressable in a secondary memory address space, wherein said host processing subsystem includes a CPU and a first cache memory which caches memory locations of said secondary memory address space for said CPU, said first cache memory having a line size of l bytes, said host processing subsystem operating to return, in response to a secondary memory line address specified to said host processing subsystem and the assertion of an inquiry signal to said host processing subsystem, a hit modified indication of whether the specified secondary memory line is cached in a modified state in said first cache memory, and wherein said bus master transfers data with said memory locations according to a transaction protocol in which said bus master specifies a starting data unit address for said transaction, comprising, in response to initiation of a first transaction and specification by said bus master of a first starting address being the data unit address in the secondary memory address space of a first starting data unit, the steps of: specifying to said host processing subsystem, the line address of an N'th l-byte line of said secondary memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said secondary memory address space which includes said first starting data unit, after receiving said hit modified indication from said host processing subsystem in response to said inquiry signal, indicating that said N'th l-byte line of said secondary memory address space is cached in a modified state, transferring data units between said bus master and memory locations in said secondary memory address space according to said first transaction; and after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said host processing subsystem the line address of the N+1'th l-byte line of said secondary memory address space and asserting said inquiry signal a second time. ### Claim 11 (depends on 10) A method according to claim 10, wherein in said transaction protocol, data units are transferred sequentially after said bus master specifies a starting data unit, until said transaction is terminated, no further address specification by said bus master being necessary during said transaction. ### Claim 12 (depends on 10) A method according to claim 10, wherein said bus master is a PCI bus master, and wherein said initiation of a first transaction comprises assertion by said bus master of the PCI-bus FRAME# and IRDY# signals. ### Claim 13 (depends on 10) A method according to claim 10, further comprising, if said hit modified indication from said host processing subsystem is asserted in response to said first assertion of said inquiry signal, the step of awaiting completion of a write-back cycle by said host processing subsystem prior to said step of transferring data units. ### Claim 14 (depends on 10) A method according to claim 10, wherein said hit modified indication is considered received on an n'th rising edge transition of a clock signal which occurs after said first assertion of said inquiry signal, n being a predefined integer greater than 0. ### Claim 15 (depends on 10) A method according to claim 10, wherein said first starting data unit is not the highest data unit in said N'th l-byte line of said secondary memory address space. ### Claim 16 (depends on 10) A method according to claim 10, wherein in said transaction protocol, data units are transferred sequentially after said bus master specifies a starting data unit, until said transaction is terminated, and wherein said first transaction is not terminated prior to the transfer of the first data unit in said N+1'th l-byte line of said secondary memory address space. ### Claim 17 (depends on 10) A method according to claim 10, wherein in said transaction protocol, data units are transferred sequentially after said bus master specifies a starting data unit, until said transaction is terminated, and wherein, if said host processing subsystem returns said hit modified indication unasserted in response to said second assertion of the inquiry signal, said first transaction is not terminated prior to the transfer of the first data unit in said N+1'th l-byte line of said secondary memory address space. ### Claim 18 (depends on 17) A method according to claim 17, further comprising, if said first transaction is not terminated prior to the transfer of the first data unit in said N+1'th l-byte line of said secondary memory address space, the step of, after transfer of the last data unit in said Nth l-byte line of said secondary memory address space, and before transfer of the last data unit in said N+1'th l-byte line of said secondary memory address space, specifying to said host processing subsystem the line address of the N+2'th l-byte line of said secondary memory address space and asserting said inquiry signal a third time. ### Claim 19 (depends on 18) A method according to claim 18, wherein, if said host processing subsystem returns said hit modified indication unasserted in response to said third assertion of said inquiry signal, said first transaction is not terminated prior to the transfer of the first data unit in said N+2'th l-byte line of said secondary memory address space. ### Claim 20 A method for use with a first processing subsystem, a second processing subsystem and memory locations addressable in a memory address space, wherein said first processing subsystem includes a first address-providing unit and a first cache memory which caches memory locations of said memory address space for said first address-providing unit, said first cache memory having a line size of l bytes, said first processing subsystem operating to return, in response to a memory line address specified to said first processing subsystem and the assertion of an inquiry signal (EADS#) to said first processing subsystem, a hit modified indication of whether the specified memory line is cached in a modified state in said first cache memory, and wherein said second processing subsystem transfers data with said memory locations according to a transaction protocol in which said second processing subsystem specifies a starting data unit address for said transaction, comprising, in response to specification by said second processing subsystem of a first starting address being the data unit address in the memory address space of a first starting data unit, and initiation of a first transaction, the steps of: specifying to said first processing subsystem, the line address of an N'th l-byte line of said memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said memory address space which includes said first starting data unit; after receiving said hit modified indication from said first processing subsystem in response to said inquiry signal, transferring data units between said second processing subsystem and memory locations in said memory address space according to said first transaction; and after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said first processing subsystem the line address of the N+1'th l-byte line of said memory address space and asserting said inquiry signal a second time. ### Claim 21 Apparatus for transferring a plurality of data units between a bus master and a respective plurality of memory locations at sequential memory location addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising: means for sequentially transferring data units between said bus master and said secondary memory beginning at a starting memory location address in said secondary memory address space and continuing beyond an l-byte boundary of said secondary memory address space, said sequentially transferred data units including a last data unit before said l-byte boundary and a first data unit beyond said l-byte boundary; and means for initiating a next-line inquiry, prior to completion of the transfer of the last data unit before said l-byte boundary, to determine whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being a line of said secondary memory which includes said first data unit beyond said l-byte boundary. ### Claim 22 (depends on 21) Apparatus according to claim 21, further comprising means for, if said next-line inquiry determines that said N+1'th l-byte line of secondary memory is cached in a modified state in said first cache memory: stopping said step of sequentially transferring data units at said l-byte boundary; and continuing said step of sequentially transferring data units beyond said l-byte boundary after a write-back of said N+1'th l-byte line from said first cache memory to said secondary memory. ### Claim 23 (depends on 21) Apparatus according to claim 21, wherein said secondary memory includes a tertiary memory and further includes a second cache memory which caches memory locations of said tertiary memory for said host processing unit and said first cache memory in combination. ### Claim 24 (depends on 21) Apparatus according to claim 21, wherein said starting memory location address is not the address of the last data unit before said l-byte boundary, further for transferring a second plurality of data units between said bus master and a second respective plurality of memory locations at sequential memory location addresses in said secondary memory address space, beginning with a second starting memory location address which is the address of the highest data unit in an M'th l-byte line of said secondary memory, further comprising: means for transferring said highest data unit between said bus master and said secondary memory; means for initiating a second inquiry to determine weather the M+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said second inquiry returning negatively if the M+1'th l-byte line is not cached in the modified state in and issuing a write-back cycle if the M+1'th l-byte line is cached in a modified state; and means for sequentially transferring data units between said bus master and said secondary memory beginning at the first memory location address in said M+1'th l-byte line only after said second inquiry returns negatively or said write-back cycle completes, whichever occurs in response to said second inquiry. ### Claim 25 (depends on 21) Apparatus according to claim 21, wherein said bus master is a PCI bus master, wherein said first cache memory includes an instruction cache and a data cache, and wherein said host processing unit and said first cache memory are fabricated on a single CPU chip. ### Claim 26 Apparatus for transferring data between a bus master and a plurality of memory locations at respective addresses in an address space of a secondary memory, for use with a host processing unit and a first cache memory which caches memory locations of said secondary memory for said host processing unit, said first cache memory having a line size of l bytes, comprising: means for sequentially transferring at least three data units between said bus master and said secondary memory beginning at a first starting memory location address in said secondary memory address space and continuing sequentially beyond an l-byte boundary of said secondary memory address space; and means for, prior to completion of the transfer of the first data unit beyond said l-byte boundary, determining whether an N+1'th l-byte line of said secondary memory is cached in a modified state in said first cache memory, said N+1'th l-byte line being the line of said secondary memory which includes said first data unit beyond said l-byte boundary, said means for sequentially transferring, transferring all of said data units at a constant rate. ### Claim 27 Apparatus comprising a host processing subsystem, a bus master and memory locations addressable in a secondary memory address space, wherein said host processing subsystem includes a CPU and a first cache memory which caches memory locations of said secondary memory address space for said CPU, said first cache memory having a line size of l bytes, said host processing subsystem operating to return, in response to a secondary memory line address specified to said host processing subsystem and the assertion of an inquiry signal to said host processing subsystem, a hit modified indication of whether the specified secondary memory line is cached in a modified state in said first cache memory, and wherein said bus master transfers data with said memory locations according to a transaction protocol in which said bus master specifies a starting data unit address for said transaction, said apparatus further comprising: means for specifying to said host processing subsystem, the line address of an N'th l-byte line of said secondary memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said secondary memory address space which includes a first starting data unit specified by said bus master in initiating a first transaction, means for, after receiving said hit modified indication from said host processing subsystem in response to said inquiry signal, indicating that said N+1'th l-byte line of said secondary memory address space is cached in a modified state, transferring data units between said bus master and memory locations in said secondary memory address space according to said first transaction; and means for, after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said host processing subsystem the line address of the N+1'th l-byte line of said secondary memory address space and asserting said inquiry signal a second time. ### Claim 28 (depends on 27) Apparatus according to claim 27, wherein in said transaction protocol, data units are transferred sequentially after said bus master specifies a starting data unit, until said transaction is terminated, no further address specification by said bus master being necessary during said transaction. ### Claim 29 (depends on 27) Apparatus according no claim 27, wherein said bus master is a PCI bus master, and wherein said initiation of a first transaction comprises assertion by said bus master of PCI-bus FRAME# and IRDY# signals. ### Claim 30 (depends on 27) Apparatus according to claim 27, wherein, if said hit modified indication from said host processing subsystem is asserted in response to said first assertion of said inquiry signal, said means for transferring data units awaits completion of a write-back cycle by said host processing subsystem prior to transferring data units according to said first transaction. ### Claim 31 (depends on 27) Apparatus according to claim 27, wherein said hit modified indication is considered received on an n'th rising edge transition of a clock signal which occurs after said first assertion of said inquiry signal, n being a predefined integer greater than 0. ### Claim 32 (depends on 27) Apparatus according to claim 27, wherein said first starting data unit is not the highest data unit in said N'th l-byte line of said secondary memory address space. ### Claim 33 (depends on 27) Apparatus according to claim 27, wherein in said transaction protocol, data units are transferred sequentially after said bus master specifies a starting data unit, until said transaction is terminated, and wherein said first transaction is not terminated prior to the transfer of the first data unit in said N+1'th l-byte line of said secondary memory address space. ### Claim 34 (depends on 27) Apparatus according to claim 27, wherein in said transaction protocol, data units are transferred sequentially after said bus master specifies a starting data unit, until said transaction is terminated, and wherein, if said host processing subsystem returns said hit modified indication unasserted in response to said second assertion of the inquiry signal, said first transaction is not terminated prior to the transfer of the first data unit in said N+1'th l-byte line of said secondary memory address space. ### Claim 35 Apparatus for use with a first processing subsystem, a second processing subsystem and memory locations addressable in a memory address space, wherein said first processing subsystem includes a first address-providing unit and a first cache memory which caches memory locations of said memory address space for said first address-providing unit, said first cache memory having a line size of l bytes, said first processing subsystem operating to return, in response to a memory line address specified to said first processing subsystem and the assertion of an inquiry signal to said first processing subsystem, a hit modified indication of whether the specified memory line is cached in a modified state in said first cache memory, and wherein said second processing subsystem transfers data with said memory locations according to a transaction protocol in which said second processing subsystem specifies a starting data unit address for said transaction, comprising: means for specifying to said first processing subsystem, the line address of an N'th l-byte line of said memory address space and asserting said inquiry signal a first time, said N'th l-byte line being the line of said memory address space which includes a first starting data unit specified by said second processing subsystem in initiating a first transaction; means for, after receiving said hit modified indication from said first processing subsystem in response to said inquiry signal, transferring data units between said second processing subsystem and memory locations in said memory address space according to said first transaction; and means for, after receiving said hit modified indication, but not in response to completion of any transfer of said first transaction, specifying to said first processing subsystem the line address of the N+1'th l-byte line of said memory address space and asserting said inquiry signal a second time.