# US 5,710,780 A · Digital circuitry with improved parallel signature analysis capability > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,710,780 A - Document ID: US5710780A - Status: Granted - Kind: A - Application number: 08/695,139 - Filed: 1996-08-08 - Granted: 1998-01-20 - Earliest claimed: 1994-05-26 - Assignees: Texas Instruments Incorporated - Inventors: Sudha Thiruvengadam - Web page: https://patentgrep.com/patent/US5710780A ## CPC - G06F 11/27: Built-in tests - G06F 2201/83: the solution involving signatures - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Digital circuitry (11) in a data processing system (10) includes parallel signature analysis circuitry (49, 49A) having a sampling feature (51, 53, 89) which permits sampling any given signal on all clock phases of the digital circuitry. ## Claims ### Claim 1 A data processing system, comprising: a data processing device including data processing circuitry for performing data processing operations on data provided thereto, said data processing circuitry having a plurality of clock signal paths for carrying respective clock signals; and a peripheral device connected to said data processing device for communication with said data processing device; said data processing device having a parallel signature analysis circuit including a plurality of latch circuits, each said latch circuit including a data input and a data output, a first said latch circuit having said data output thereof coupled to the data input of a second said latch circuit, and said first latch circuit having said data input thereof coupled to the data output of a third said latch circuit; said parallel signature analysis circuit including a predetermined sample nodes associated with a circuit node driven by said data processing circuitry, sample circuitry which is coupled to said clock signal paths and which can be triggered by any of said clock signals to sample a logic state of said circuit node and to output the sampled logic state on said predetermined sample node regardless of which of said clock signals triggers said sample circuitry, and circuitry for selectively coupling said data input of said first latch circuit to said predetermined sample node. ### Claim 2 (depends on 1) The system of claim 1, including a multiplexer having a plurality of data inputs respectively connected to said clock signal paths and having an output connected to said sample circuitry. ### Claim 3 (depends on 2) The system of claim 2, wherein said sample circuitry includes a further latch circuit having a clock input connected to said multiplexer output and having a data input connected to said circuit node and having a data output connected to said sample node. ### Claim 4 (depends on 2) The system of claim 2, wherein said circuitry for selectively coupling includes a further multiplexer having a first data input connected to said circuit node and having a second data input connected to said sample node and having an output coupled to said data input of said first latch circuit. ### Claim 5 (depends on 1) The system of claim 1, wherein said parallel signature analysis circuitry includes a further predetermined sample node associated with a further circuit node driven by said data processing circuitry, said sample circuitry further operable to sample a logic state of said further circuit node and to output the sampled logic state on said further predetermined sample node regardless of which of said clock signals triggers said sample circuitry, and wherein said circuitry for selectively coupling is further operable to selectively couple said data input of said second latch circuit to said further predetermined sample node. ### Claim 6 (depends on 1) The system of claim 1, wherein said sample circuitry includes a further latch circuit having a clock input coupled to said clock signal paths and having a data input connected to said circuit node and having a data output connected to said sample node. ### Claim 7 (depends on 6) The system of claim 6, wherein said circuitry for selectively coupling includes a multiplexer having a first data input connected to said circuit node and having a second data input connected to said sample node and having an output coupled to said data input of said first latch circuit. ### Claim 8 (depends on 1) The system of claim 1, wherein said circuitry for selectively coupling includes a multiplexer having a first data input connected to said circuit node and having a second data input connected to said sample node and having an output coupled to said data input of said first latch circuit. ### Claim 9 (depends on 8) The system of claim 8, wherein said circuitry for selectively coupling further includes an exclusive-OR circuit having an input connected to said output of said multiplexer and having an output connected to said data input of said first latch circuit. ### Claim 10 An electronic device, comprising: data processing circuitry for performing data processing operations on data provided thereto, said data processing circuitry having a plurality of clock signal paths for carrying respective clock signals; and a parallel signature analysis circuit including a plurality of latch circuits, each said latch circuit including a data input and a data output, a first said latch circuit having said data output thereof coupled to the data input of a second said latch circuit, and said first latch circuit having said data input thereof coupled to the data output of a third said latch circuit; said parallel signature analysis circuit including a predetermined sample node associated with a circuit node driven by said data processing circuitry, sample circuitry which is coupled to said clock signal paths and which can be triggered by any of said clock signals to sample a logic state of said circuit node and to output the sampled logic state on said predetermined sample node regardless of which of said clock signals triggers said sample circuitry, and circuitry for selectively coupling said data input of said first latch circuit to said predetermined sample node. ### Claim 11 (depends on 10) The device of claim 10, including a multiplexer having a plurality of data inputs respectively connected to said clock signal paths and having an output connected to said sample circuitry. ### Claim 12 (depends on 11) The device of claim 11, wherein said sample circuitry includes a further latch circuit having a clock input connected to said multiplexer output and having a data input connected to said circuit node and having a data output connected to said sample node. ### Claim 13 (depends on 11) The device of claim 11, wherein said circuitry for selectively coupling includes a further multiplexer having a first data input connected to said circuit node and having a second data input connected to said sample node and having an output coupled to said data input of said first latch circuit. ### Claim 14 (depends on 10) The device of claim 10, wherein said parallel signature analysis circuitry includes a further predetermined sample node associated with a further circuit node driven by said data processing circuitry, said sample circuitry further operable to sample a logic state of said further circuit node and to output the sampled logic state on said further predetermined sample node regardless of which of said clock signals triggers said sample circuitry, and wherein said circuitry for selectively coupling is further operable to selectively couple said data input of said second latch circuit to said further predetermined sample node. ### Claim 15 (depends on 10) The device of claim 10, wherein said sample circuitry includes a further latch circuit having a clock input coupled to said clock signal paths and having a data input connected to said circuit node and having a data output connected to said sample node. ### Claim 16 (depends on 15) The device of claim 15, wherein said circuitry for selectively coupling includes a multiplexer having a first data input connected to said circuit node and having a second data input connected to said sample node and having an output coupled to said data input of said first latch circuit. ### Claim 17 (depends on 10) The device of claim 10, wherein said circuitry for selectively coupling includes a multiplexer having a first data input connected to said circuit node and having a second data input connected to said sample node and having an output coupled to said data input of said first latch circuit. ### Claim 18 (depends on 17) The device of claim 17, wherein said circuitry for selectively coupling further includes an exclusive-OR circuit having an input connected to said output of said multiplexer and having an output connected to said data input of said first latch circuit. ### Claim 19 A circuit for producing a parallel test signature from data obtained from a target circuit, comprising: a plurality of latch circuits, each said latch circuit including a data input and a data output, a first said latch circuit having said data output thereof coupled to the data input of a second said latch circuit, and said first latch circuit having said data input thereof coupled to the data output of a third said latch circuit; a predetermined sample circuitry with a node of the target circuit; sample circuitry which includes a plurality of inputs for receiving respective clock signals from the target circuit and which can be triggered by any of said clock signals to sample a logic state of said node of the target circuit and to output the sampled logic state on said predetermined sample node regardless of which of said clock signals triggers said sample circuitry; and circuitry for selectively coupling said data input of said first latch circuit to said predetermined sample node.