# US 5,710,779 A · Real time data observation method and apparatus

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- Number: US 5,710,779 A
- Document ID: US5710779A
- Status: Granted
- Kind: A
- Application number: 08/643,444
- Filed: 1996-05-08
- Granted: 1998-01-20
- Earliest claimed: 1996-04-09
- Assignees: Texas Instruments Incorporated
- Inventors: Lee D. Whetsel
- Web page: https://patentgrep.com/patent/US5710779A

## CPC

- G01R 31/318541: {Scan latches or cell details}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A scan cell design includes a bypass mode in which the scan input (SI) of the cell is connected directly to the scan output of the cell by a connection that bypasses the scan memory (M1) of the cell.

## Claims

### Claim 1

A method of operating a plurality of series-connected scan cells, each scan cell operable to capture and scan signals from a target circuit to be observed, comprising the steps of:
placing one of the scan cells in an observation mode wherein scanning operation thereof is disabled and wherein a data node thereof which is connected to the target circuit is also connected directly to a scan output of said one scan cell to permit the target circuit to drive the scan output directly via the data node;
placing another of the scan cells in a bypass mode wherein a scan output thereof is connected directly to a scan input thereof, so that said one scan cell is in the observation mode while said another scan cell is in the bypass mode; and
observing, at the scan output of said another scan cell, signal activity occurring at the data node of said one scan cell while said one scan cell is in the observation mode with scanning operation thereof disabled.

### Claim 2 (depends on 1)

The method of claim 1, wherein said first-mentioned placing step includes scanning configuration information through the plurality of series-connected scan cells.

### Claim 3 (depends on 1)

The method of claim 1, wherein said last-mentioned placing step includes scanning configuration information through the plurality of series-connected scan cells.

### Claim 4 (depends on 1)

The method of claim 1, wherein both of said placing steps include scanning configuration information through the plurality of series-connected scan cells.

### Claim 5 (depends on 1)

The method of claim 1, wherein said another scan cell is adjacent the one scan cell in the series-connected plurality of scan cells.

### Claim 6 (depends on 5)

The method of claim 5, wherein said observing step includes passing the signal activity through both of said scan cells.

### Claim 7 (depends on 1)

The method of claim 1, including placing in the bypass mode each of a group of consecutive scan cells within the plurality of series-connected scan cells, the group including said another scan cell.

### Claim 8 (depends on 7)

The method of claim 7, wherein said observing step includes passing the signal activity through said one scan cell and each scan cell of the group.

### Claim 9 (depends on 1)

The method of claim 1, wherein the data node is a data input of said one scan cell.

### Claim 10

A scan cell, comprising:
a scan input;
a data input connected to a target circuit to be observed;
a scan output;
a memory circuit connected between said scan input and said scan output and also connected between said data input and said scan output; and
said data input directly connectable to said scan output.

### Claim 11 (depends on 10)

The scan cell of claim 10, wherein said scan cell is a boundary scan cell.

### Claim 12 (depends on 11)

The scan cell of claim 11, wherein said target circuit includes a bond pad of an integrated circuit, and wherein said data input is connected to said bond pad during normal operation of said target circuit.

### Claim 13 (depends on 10)

The scan cell of claim 10, wherein said memory circuit is part of the target circuit.

### Claim 14 (depends on 10)

The scan cell of claim 10, including a multiplexer having a first data input connected to said scan input, having a second data input connected to an output of said memory circuit, having a third data input connected to said first-mentioned data input and having a data output connected to said scan output.

### Claim 15 (depends on 14)

The scan cell of claim 14, including a further memory circuit having an input connected to said output of said first-mentioned memory circuit and having an output connected to a control input of said multiplexer.

### Claim 16 (depends on 15)

The scan cell of claim 15, wherein said further memory circuit includes a bus holder circuit and a switch connected between said bus holder circuit and said input of said further memory circuit.

### Claim 17 (depends on 14)

The scan cell of claim 14, wherein said memory circuit output is connected to a control input of said multiplexer.

### Claim 18 (depends on 10)

The scan cell of claim 10, including a multiplexer having a first data input connected to said first-mentioned data input, having a second data input connected to said scan input, and having a data output connected to an input of said memory circuit.

### Claim 19

Electronic circuitry, comprising:
a plurality of interconnected circuits, each said circuit including functional circuitry for performing normal operating functions of the circuit, and each said circuit including a scan path for communication with said functional circuitry, said scan path having a scan input and a scan output;
said scan output of a first said circuit connectable to said scan input of a second said circuit, and said scan output of said second circuit connectable to said scan input of a third said circuit; and
each of said scan outputs of said first and second circuits also connectable to a single node which is separate from said scan inputs of said second and third circuits.

### Claim 20 (depends on 10)

The circuitry of claim 10, wherein said circuits are integrated circuits.

### Claim 21

A scan cell, comprising:
a scan input;
a data input connected to a target circuit to be observed;
a scan output;
a memory circuit having an output coupled to said scan output, and having an input;
a selector connected between said scan input and said memory circuit input and also connected between said data input and said memory circuit input, said selector operable to connect either selected one of said scan input and said data input to said memory circuit input in response to a scan control signal that indicates which of said scan input and said data input is selected for connection to said memory circuit input; and
said scan input directly connectable to said scan output via a direct connection that is independent of said memory circuit, said direct connection including a switch which breaks said direct connection in response to selection of said scan input by said scan control signal.

### Claim 22 (depends on 21)

The scan cell of claim 21, wherein said switch is further operable in response to selection of said scan input by said scan control signal to connect said memory circuit output to said scan output.

### Claim 23 (depends on 22)

The scan cell of claim 22, wherein said switch is a multiplexer having a control input coupled to said scan control signal.