# US 5,710,770 A · ATM cell switching system

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- Number: US 5,710,770 A
- Document ID: US5710770A
- Status: Granted
- Kind: A
- Application number: 08/462,532
- Filed: 1995-06-05
- Granted: 1998-01-20
- Earliest claimed: 1987-07-15
- Assignees: Hitachi, Ltd.
- Inventors: Takahiko Kozaki; Junichirou Yanagi; Kiyoshi Aiki; Yutaka Ito; Kaoru Aoki; Shinobu Gohara
- Web page: https://patentgrep.com/patent/US5710770A

## CPC

- H04L 12/5601: {Transfer mode dependent, e.g. ATM}
- H04J 3/247: {ATM or packet multiplexing}
- H04L 12/5602: {Bandwidth control in ATM Networks, e.g. leaky bucket}
- H04L 45/04: {Interdomain routing, e.g. hierarchical routing}
- H04L 49/108: {using shared central buffer}
- H04L 49/203: {ATM switching fabrics with multicast or broadcast capabilities}
- H04L 49/255: {Control mechanisms for ATM switching fabrics}
- H04L 49/256: {Routing or path finding in ATM switching fabrics}
- H04L 49/3081: {ATM peripheral units, e.g. policing, insertion or extraction}
- H04Q 11/0478: {Provisions for broadband connections}
- H04L 2012/5627: {Fault tolerance and recovery}
- H04L 2012/5631: {Resource management and allocation}
- H04L 2012/5638: {Services, e.g. multimedia, GOS, QOS}
- H04L 2012/5649: {Cell delay or jitter}
- H04L 2012/565: {Sequence integrity}
- H04L 2012/5651: {Priority, marking, classes}
- H04L 2012/5652: {Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly}
- H04L 2012/5672: {Multiplexing, e.g. coding, scrambling}
- H04L 2012/5679: {Arbitration or scheduling}
- H04L 2012/568: {Load balancing, smoothing or shaping}
- H04L 2012/5681: {Buffer or queue management}
- H04L 2012/5682: {Threshold; Watermark}
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)
- H04J: MULTIPLEX COMMUNICATION (transmission in general H04B; peculiar to transmission of digital information H04L5/00; systems for the simultaneous or sequential transmission of more than one television signal H04N7/08; in exchanges H04Q11/00; stereophonic systems H04S)
- H04Q: SELECTING (switches, relays, selectors H01H; wireless communication networks H04W)

## Abstract

An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory. The buffer memory control circuit has a control table device for outputting an identifier of an output line to which the cells read from the shared buffer memory are to be outputted, and cells are read from the chain designated by the output line identifier outputted from the control table device.

## Claims

### Claim 1

A switching system comprising:
a shared buffer memory for storing a plurality of fixed length packets;
means for supplying fixed length input packets received from a plurality of input lines to said buffer memory, each of said input packets including routing information for designating one of a plurality of output lines and a connection identifier for designating a virtual connection or a virtual path of the packet;
means for distributing output packets read out from said buffer memory to said plurality of output lines in a predetermined order;
means for writing in said buffer memory a pair of data including a packet and a pointer address for indicating an address location of a succeeding packet in accordance with the routing information and the connection identifier of the input packets;
means for assigning connection identifiers to time slots of each of the output lines so that a set of same connection identifiers has a predetermined frequency corresponding to a bandwidth of the communication carried out by the packets having the same connection identifier;
means for designating one of the output lines periodically;
means for designating the location address of a packet to be read out from said buffer memory in accordance with one of said assigned connection identifiers which is specified depending on a present time slot on said designated output line and reading out from said buffer memory a pair of data including a packet and a pointer address in accordance with said designated location address to supply the packet to said distributing means as said output packet; and
means for storing the pointer address read out from said buffer memory as a new location address for use in the designating of the location address carried out later.

### Claim 2 (depends on 1)

A switching system according to claim 1 wherein said designating means includes means for examining another location address corresponding to another of said assigned connection identifiers corresponding to a time slot other than the present time slot if no packet exists in the location address corresponding to the time slot of the one of said assigned connection identifiers, whereby if a packet exists at said another location address corresponding to said another of said connection identifiers, the packet is read out from the location address corresponding to said another of said connection identifiers to be supplied to said distributing means.

### Claim 3 (depends on 1)

A switching system according to claim 1 wherein said connection identifier comprises at least a part of a virtual path identifier designating a virtual path, at least a part of a virtual channel identifier or part of a combination of the virtual path identifier and the virtual channel identifier.

### Claim 4 (depends on 1)

A switching system according to claim 1, wherein at least one list structure is formed to store a series of input packets classified in accordance with the combination of connection identifier and additional information other than the connection identifier.

### Claim 5 (depends on 4)

A switching system according to claim 4, wherein the additional information includes at least a part of bits indicative of an identification number of the output line.

### Claim 6 (depends on 4)

A switching system according to claim 4, wherein the additional information includes information indicative of a priority of the input packets.

### Claim 7 (depends on 4)

A switching system according to claim 4, wherein the additional information includes at least a part of bits indicative of an identification number of a low-speed output line when the output packets are demultiplexed to the low-speed line.