# US 5,710,742 A · High density two port SRAM cell for low voltage CMOS applications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,710,742 A - Document ID: US5710742A - Status: Granted - Kind: A - Application number: 08/440,285 - Filed: 1995-05-12 - Granted: 1998-01-20 - Earliest claimed: 1995-05-12 - Assignees: International Business Machines Corporation - Inventors: Eric Lee Carter; Roger Paul Gregor; Moon Ho Lee; Michael Richard Ouellette - Web page: https://patentgrep.com/patent/US5710742A ## CPC - G11C 8/16: Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups - G11C 11/412: using field-effect transistors only - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A two-port memory cell design which permits simultaneous reading and writing of cells which are on the same wordline but on different Bit Select lines without increase in Read Access Time, and while maintaining memory functionality at low voltages. The memory cell uses a standard 6 transistor design to provide a differential read for fast access plus another three transistors are added to each cell to provide a means of differentially writing the cell and de-gating the write if the bit-select is not active. This cell design has applicability to multi-port memories as well. ## Claims ### Claim 1 An apparatus, comprising: a plurality of memory cells each including latch means for storing a data bit; receiving means coupled to each of the memory cells for transmitting data bits to be stored in selected ones of the memory cells, the receiving means comprising write bit lines and a write word line; and the memory cells each further including: input means having only three transistors for transmitting the data bit from the receiving means to the latch means, wherein only one of said only three transistors is directly connected both to the write word line and to ground. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein two others of said only three transistors are coupled in parallel both to said only one of the three transistors and to the latch means. ### Claim 3 (depends on 1) The apparatus according to claim 1, further comprising control means for controlling data bit storage, the control means including a pair of AND gates each coupled to a separate one of a pair of said write bit lines and to a decoder for communicating control information to said pair of AND gates, the pair of write bit lines both coupled to a portion of the plurality of memory cells. ### Claim 4 An electronic memory cell, comprising: a latch circuit for storing a data bit; a word line and a bit line for providing to the latch circuit the data bit; and only one transistor connected directly to the word line and directly to ground for controlling a reception of the data bit. ### Claim 5 (depends on 4) The electronic memory cell according to claim 4 further comprising a second bit line, and a pair of transistors coupled in parallel both to the one transistor and to the latch circuit, one of the pair of transistors further coupled to the bit line and another of the pair of transistors coupled to the second bit line. ### Claim 6 (depends on 5) The electronic memory cell according to claim 5, wherein the one transistor and the pair of transistors are all NFETs. ### Claim 7 In an electronic memory apparatus comprising a plurality of memory cells, and having write word lines and write bit lines for selectively accessing the memory cells to write data bits thereto, the improvement comprising: only one grounded transistor that is both coupled to a memory cell and connected directly to a write word line for coupling the memory cell to the write word line. ### Claim 8 (depends on 7) The improvement of claim 7 wherein the memory cell includes: a latch for storing a data bit written thereto; and a pair of transistors coupled in parallel both directly to the latch and the grounded transistor. ### Claim 9 (depends on 8) The improvement according to claim 8, wherein the pair of transistors is each further coupled directly to a separate one of the write bit lines. ### Claim 10 A random access memory, comprising: memory cells, each including: a latch circuit for storing a datum (0 or 1); and an input circuit coupled to the latch circuit for receiving the datum, the input circuit including first, second, and third switching devices, the first and second switching devices coupled in parallel both to the latch circuit and to the third switching device, the third switching device coupled directly to ground; write bit lines and write word lines for selectively transmitting data to the memory cells; and the first and second switching devices each coupled to a separate one of the write bit lines, the third switching device further coupled directly to a write word line. ### Claim 11 (depends on 1) The apparatus according to claim 1 wherein the write bit lines include a pair of complimentary write bit lines. ### Claim 12 (depends on 2) The apparatus according to claim 2, wherein said two others of said only three transistors are each further coupled to a separate one of the write bit lines. ### Claim 13 (depends on 5) The electronic memory cell according to claim 5 wherein the bit line and the second bit line are complimentary bit lines. ### Claim 14 (depends on 5) The electronic memory cell according to claim 5 further comprising control means for controlling data bit storage, the control means including: a pair of AND gates, one of the AND gates coupled to the bit line and another of the AND gates coupled to the second bit line; and a decoder for communicating control information to said pair of AND gates. ### Claim 15 (depends on 7) The improvement of claim 7, further comprising control means for controlling data bit storage, the control means including a pair of AND gates each coupled to a separate one of a pair of said write bit lines, the pair of write bit lines both coupled to a same portion of the plurality of memory cells. ### Claim 16 (depends on 10) The random access memory according to claim 10, further comprising control means for controlling data bit storage, the control means including a pair of AND gates each coupled to a separate one of a pair of said write bit lines and to a decoder for communicating control information to said pair of AND gates, the pair of write bit lines both coupled to a same portion of the memory cells. ### Claim 17 An apparatus, comprising: a plurality of memory cells each including latch means for storing a data bit; receiving means coupled to each of the memory cells for transmitting data bits to be stored in selected ones of the memory cells, the receiving means comprising write bit lines and a write word line; the memory cells each further including: input means coupled to the receiving means for transmitting the data bit to the latch means, the input means including an input transistor coupled to the receiving means and to ground; and control means for controlling data bit storage, the control means including a pair of AND gates each coupled to a separate one of a pair of said write bit lines, the pair of write bit lines both coupled to a portion of the plurality of memory cells. ### Claim 18 An apparatus, comprising: a plurality of memory cells each including latch means for storing a data bit; receiving means coupled to each of the memory cells for transmitting data bits to be stored in selected ones of the memory cells, the receiving means comprising write bit lines and a write word line; and the memory cells each further including: input means, for transmitting the data bit from the receiving means to the latch means, having an input transistor coupled to the receiving means and directly to ground, and a pair of transistors coupled in parallel both to the input transistor and to the latch means, and the pair of transistors each further coupled directly to a separate write bit line.