# US 5,710,740 A · Circuit including DRAM and voltage regulator, and method of increasing speed of operation of a DRAM > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,710,740 A - Document ID: US5710740A - Status: Granted - Kind: A - Application number: 08/717,836 - Filed: 1996-09-23 - Granted: 1998-01-20 - Earliest claimed: 1995-06-27 - Assignees: Micron Technology, Inc. - Inventors: Troy A. Manning - Web page: https://patentgrep.com/patent/US5710740A ## CPC - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An integrated circuit comprising a reference voltage generator having an output providing a reference voltage; a selectively engageable filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed or refreshed in response to a first signal; and a timing circuit which engages the filter in response to presence of a first signal, and causes the filter to filter the reference voltage. A method of increasing the speed of operation of an integrated circuit including a dynamic random access memory having memory cells which are individually accessed in response to a signal, including a reference voltage generator having an output, and including a voltage regulator which accepts the output of the reference voltage generator and supplies voltage to the dynamic random access memory, the method comprising filtering the output of the reference voltage generator in response to the signal. ## Claims ### Claim 1 A circuit comprising: a reference voltage generator having an output configured to provide a DC reference voltage;. a dynamic random access memory having a memory cell which is selectively refreshed in response to a signal; a voltage regulator having an input, and having an output which supplies an operating voltage to the dynamic random access memory; and a selectively engageable filter having an output coupled to the input of the voltage regulator, and having an input coupled to the output of the reference voltage generator, the filter being engaged to filter the reference voltage during refreshing of the memory cell. ### Claim 2 (depends on 1) A circuit in accordance with claim 1 wherein the filter filters the output of the reference voltage generator in response to the signal. ### Claim 3 (depends on 1) A circuit in accordance with claim 1 wherein the filter comprises a low pass filter. ### Claim 4 A circuit comprising: a dynamic random access memory having a memory cell which is selectively refreshed in response to a RAS signal; a voltage regulator having an input, and having an output which supplies an operating voltage to the dynamic random access memory; and a selectively engageable filter having an output coupled to the input of the voltage regulator and having an input adapted to be coupled to a reference voltage, the filter being engaged to filter the reference voltage during refreshing of the memory cell. ### Claim 5 (depends on 1) A circuit in accordance with claim 1 and further comprising an integrated circuit package housing the dynamic random access memory, the voltage regulator, and the filter. ### Claim 6 A circuit comprising: a dynamic random access memory having a memory cell which is selectively refreshed in response to a signal, the memory cell including a first plate adapted to be coupled to a first voltage and a second cell selectively coupled to an upper voltage higher than the first voltage to write data of a first value to the cell, or coupled to a lower voltage lower than the first voltage to write data of a second value to the cell; a voltage regulator connected to supply the upper voltage to the dynamic random access memory; and a selectively engageable filter configured to impede reduction of the upper voltage during refreshing of the memory cell. ### Claim 7 (depends on 6) A circuit in accordance with claim 6 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage generator, and wherein the filter filters the output of the reference voltage generator in response to the signal. ### Claim 8 (depends on 6) A circuit in accordance with claim 6 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage regulator, and wherein the filter comprises a low pass filter filtering the output of the reference voltage generator. ### Claim 9 A circuit comprising: a dynamic random access memory having a memory cell which is selectively refreshed in response to a RAS signal: a voltage regulator which supplies an operating voltage to the dynamic random access memory; and a selectively engageable filter configured to maintain the operating voltage steady during refreshing of the memory cell. ### Claim 10 (depends on 6) A circuit in accordance with claim 6 and further comprising an integrated circuit package housing the dynamic random access memory, the voltage regulator, and the filter. ### Claim 11 A circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable low pass filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are refreshed in response to a signal; and a timing circuit which engages the filter in response to the signal, the filter tinkering the reference voltage for a period of time during which the signal is present. ### Claim 12 (depends on 11) An integrated circuit in accordance with claim 11 wherein the filter comprises a resistor-capacitor network. ### Claim 13 (depends on 11) An integrated circuit in accordance with claim 11 wherein the memory cells are refreshed in response to a RAS signal. ### Claim 14 A circuit comprising: a reference voltage generator having an output configured to provide a DC reference voltage; a dynamic random access memory having a memory cell which is selectively accessed in response to a signal; a voltage regulator having an input, and having an output which supplies an operating voltage to the dynamic random access memory; and a selectively engageable filter having an output coupled to the input of the voltage regulator and having an input coupled to the output of the reference generator, the filter being engaged to filter the reference voltage during accessing of the memory cell. ### Claim 15 (depends on 14) A circuit in accordance with claim 14 wherein the filter filters the output of the reference voltage generator in response to the signal. ### Claim 16 (depends on 14) A circuit in accordance with claim 14 wherein the filter comprises a low pass filter. ### Claim 17 A circuit comprising: a dynamic random access memory having a memory cell which is selectively accessed in response to a RAS signal: a voltage regulator having an input, and having an output which supplies an operating voltage to the dynamic random access memory; and a selectively engageable filter having an output coupled to the input of the voltage regulator, and having an input adapted to be coupled to a reference voltage, the filter being engaged to filter the reference voltage during accessing of the memory cell. ### Claim 18 (depends on 14) A circuit in accordance with claim 14 and further comprising an integrated circuit package housing the dynamic random access memory, the voltage regulator, and the filter. ### Claim 19 A circuit comprising: a dynamic random access memory having a memory cell which is selectively accessed in response to a signal, the memory cell including a first plate adapted to be coupled to a first voltage and a second cell selectively coupled to an upper voltage higher than the first voltage to write data of a first value to the cell, or coupled to a lower voltage lower than the first voltage to write data of a second value to the cell; a voltage regulator connected to supply the upper voltage to the dynamic random access memory; and a selectively engageable filter configured to impede reduction of the upper voltage during accessing of the memory cell. ### Claim 20 (depends on 19) A circuit in accordance with claim 19 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage generator, and wherein the filter filters the output of the reference voltage generator in response to the signal. ### Claim 21 (depends on 19) A circuit in accordance with claim 19 and further comprising a reference voltage generator including an output providing a reference voltage, wherein the voltage regulator accepts the output of the reference voltage regulator, and wherein the filter comprises a low pass filter filtering the output of the reference voltage generator. ### Claim 22 A circuit comprising: a dynamic random access memory having a memory cell which is selectively accessed in response to a RAS signal: a voltage regulator which supplies an operating voltage to the dynamic random access memory; and a selectively engageable filter configured to maintain the operating voltage steady during accessing of the memory cell. ### Claim 23 (depends on 19) A circuit in accordance with claim 19 and further comprising an integrated circuit package housing the dynamic random access memory, the voltage regulator, and the filter. ### Claim 24 A circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable low pass filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed in response to a signal; and a timing circuit which engages the filter in response to the signal, the filter filtering the reference voltage for a period of time during which the signal is present. ### Claim 25 (depends on 24) An integrated circuit in accordance with claim 24 wherein the filter comprises a resistor-capacitor network. ### Claim 26 A circuit comprising: a reference voltage generator having an output providing a reference voltage; a selectively engageable low pass filter having an input connected to the output of the reference voltage generator, and having an output; a voltage regulator having an input connected to the output of the filter, and having an output; a dynamic random access memory receiving power from the output of the voltage regulator, the dynamic random access memory having memory cells that are accessed in response to a RAS signal; and a timing circuit which engages the filter in response to the signal, the filter filtering the reference voltage for a period of time during which the signal is present.